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if digitizing subsystem AD9864* rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 10 mhz to 300 mhz input fr eq uency 6.8 kh z to 27 0 khz outpu t sig nal bandwidth 7.5 db ssb nf C7.0 dbm iip3 agc fr ee range up to C34 dbm 12 db continuous a g c range 16 db front en d atten u ator baseband i/q 16-bit (or 24-bit) serial digital output lo and sampli ng clock synthesizers programmable decimation fac t or, output format, agc, an d s y the sizer sett ings 370 ? input im pedance 2.7 v to 3.6 v s u pply voltage low cu rrent co nsu m ption: 17 ma 48-lea d lfcsp package a pplic a t io ns mu ltimod e narrow-band rad i o prod u c ts analog/digital uhf/vhf f d m a receivers tetra, apco2 5 , gsm/edge portable and m o bile radio products satcom termi nals *protected by u.s. patent no. 5,969,657; o ther patents pending. pr oduc t ov er vie w the AD9864 is a g e n e ral-p u r p os e if s u bsys tem tha t dig i tizes a lo w lev e l 10 mh z t o 300 m h z if in p u t wi th a sig n al ban d wid t h ra n g in g f r o m 6. 8 kh z t o 270 kh z. the sig n al cha i n o f t h e AD9864 co n s is ts o f a lo w n o is e a m p l if ier (ln a ), a mixer , a b a nd-p a ss -? a n a l o g -to - dig i t a l co n v er ter (ad c ), a nd a de c i - m a ti o n f i l t e r w i th p r ogra m m a b l e d e ci ma ti o n fact o r . a n a u t o - ma tic ga in con t r o l (a gc) cir c u i t g i v e s t h e ad9 864 12 db o f co n t in uo us ga in ad j u s t m e n t . a u xilia r y b l o c ks inc l ude bo t h clo c k an d lo sy n t h e s i z e rs. the hig h d y namic ra n g e o f the AD9864 and inh e r e n t an t i al ias- in g p r o v ide d b y t h e b a nd-p a ss - ? con v er ter a l lo w t h e de vic e to co p e wi t h b l o c k i n g sig n als u p to 95 db s t r o n g e r tha n the desir e d sig n al . this a t tr ib u t e o f t e n r e d u ces th e cost o f a radio b y r e d u c- in g if f i l t er in g r e q u ir e m en ts. a l s o , i t ena b les m u l t imo d e rad i os of v a r y i n g ch an ne l b a nd w i d t hs , a l l o w i ng t h e i f f i lte r to b e sp e c if ie d fo r t h e la rgest cha n nel b a ndwi d t h . the s p i? p o r t p r og ra m s n u m e ro us p a ra m e t e rs o f th e AD9864, a l lo win g t h e d e vice to b e op t i m i ze d fo r a n y g i ven a p plic a t io n. p r ogra mma b l e p a ra m e ter s in c l ud e syn t h e sizer d i vid e r a tios, a g c a t te n u a t ion an d a t t a ck/d e c a y t i m e , r e ce i v e d sig n a l s t r e n g th leve l , decima t i o n fac t or , o u t p u t da ta f o r m a t , 16 db a t t e n u a t o r , a n d th e s e l e ct ed b i a s cu rr e n t s . the AD9864 is a v a i la b l e in a 48 -lead lfcs p p a c k a g e an d o p era t es f r o m a sin g le 2.7 v t o 3 . 6 v s u p p l y . th e t o tal p o w e r co n s um p t io n is ty p i ca l l y 56 m w an d a p o w e r - do wn m o de is p r o v i d ed vi a s e ri al in t e rfa c i n g. func ti onal bl oc k di a g ram - ? adc lna dac agc voltage reference spi control logic formatting/ssi decimation filter lo syn clk syn lo vco and loop filter ifin fref douta doutb fs clkout syncb pe pd pc vrefn vcm vrefp mxop mxon if2p if2n gcp gcn ?16db AD9864 clkn clkp ioutc lon lop ioutl loop filter 04319-0-001 f i g u re 1. a d 98 64 bl ock d i ag r a m
AD9864 table of contents g e neral d e s c r i p t io n ......................................................................... 3 AD9864 s p ecif ica t ion s ..................................................................... 4 dig i t a l s p e c if ic a t io n s ........................................................................ 6 a b s o l u t e m a xim u m r a t i n g s ............................................................ 7 ther mal resis t a n c e ...................................................................... 7 p i n c o nf igura t io n an d f u n c t i onal d e s c r i p t io ns .......................... 8 d e f i ni t i on o f s p e c if ica t ion s /t e s t m e t h o d s ............................... 9 t y p i cal p e r f o r ma n c e c h a r ac t e r i s t ics ........................................... 10 s e r i al p e r i ph era l i n t e r f ace (s p i ) ............................................... 15 the o r y o f o p era t io n ...................................................................... 17 s e r i al p o r t i n t e r f ace (s p i ) .......................................................... 17 s y n c hr on o u s s e r i al i n ter f ace (ss i ) ........................................... 18 s y n c r o niza t i on u s in g s y n c b .................................................. 22 i n t e r f acin g t o d s p s ..................................................................... 22 p o w e r c o n t r o l ............................................................................. 23 l o s y n t h e sizer ............................................................................ 23 f a s t a c q u ir e m o de ...................................................................... 24 c l o c k s y n t h e sizer ....................................................................... 24 if ln a/mixer ............................................................................. 26 b a nd-p a s s -? ad c . ................................................................. 27 d e cima t i o n f i l t er ....................................................................... 29 v a r i a b le ga i n a m plif ier o p era t io n w i t h a u t o ma t i c g a in c o n t r o l ......................................................................................... 30 v a r i a b le ga in c o n t r o l ................................................................ 31 a u t o ma t i c ga in c o n t r o l (a gc) . .............................................. 32 s y s t em n o is e f i gur e (nf) v e rs us v g a (o r a g c ) c o n t r o l . . 3 4 a p plica t ion s c o n s idera t ion s ..................................................... 35 s p ur io us res p on s e s . ................................................................... 37 e x t e r n al p a s s i v e c o m p on e n t re q u ir em e n ts .......................... 37 a p plica t ion s ................................................................................ 38 l a yo u t e x am ple, e v al ua t i on b o ar d , a nd s o f t wa re ................. 42 o u t l in e dim e n s io n s ....................................................................... 43 es d c a u t ion................................................................................ 43 or der i n g g u ide . ......................................................................... 43 revisi on h i s t or y rev i s i o n 0: i n i t ial v e r s i o n rev. 0 | page 2 of 4 4
AD9864 gene ral description the ad98 64 is a genera l-p u r p o s e na r r ow- b and if subsy s te m t h a t di g i t i ze s a lo w l e v e l 1 0 m h z t o 3 00 m h z if i n put w i t h a sig n a l bandwid t h r a n g ing f r om 6. 8 kh z t o 2 70 kh z. the s i g n al c h a i n o f t h e a d 9 864 consists o f an l n a, a m i xer , a b a nd - p ass - ? a d c, and a de ci m a t i on f i lter w i t h p r o g r a mmab l e de ci m a t i on f a c t o r . the i n p u t l n a is a f i xe d ga in b l o c k wi t h a n in pu t im p e dan c e of a p p r o x ima t e l y 370 ?||1.4 p f . th e ln a in p u t is s i n g le-en d ed a nd s e lf -b iasin g , al lo win g the in p u t if t o be ac-co u p l e d . th e ln a can b e dis a b l e d t h r o ug h t h e s e r i a l i n ter f a c e, p r o v idin g a f i xe d 16 db a t te n u a t io n to t h e i n p u t sig n a l . the l n a dr i v es t h e i n p u t p o r t o f a gi lb er t- typ e ac t i v e mixer . the mixer l o p o r t is dr i v en b y t h e on-chi p l o b u f f er , w h ich ca n b e dr i v en e x ter n a l ly , sin g le-ende d o r dif f er en t i a l . t h e lo b u f f er in p u ts a r e s e lf-b iasin g and al lo w th e lo in p u t t o be a c - c oupl e d . t h e op e n - c o l l e c t or output s of t h e m i x e r d r ive an ext e r n al r e s o na n t t a nk con s is t i n g o f a dif f er en t i al l c n e tw o r k t u n e d t o the if o f th e band-p a ss -? ad c. the ext e r n al dif f er en t i al lc t a n k fo r m s t h e r e s o na t o r fo r t h e f i rs t s t a g e o f t h e b a nd-p a s s -? ad c. th e t a n k l c val u es m u st be s e lec t e d f o r a cen t er f r eq uen c y o f f cl k /8, w h er e f cl k is t h e s a m p le ra t e o f th e ad c. th e f cl k /8 f r eq uen c y is th e if dig i tize d b y t h e b a nd-p a ss - ? a d c. on -chi p c a lib r a t ion a l lo ws st an - da r d t o lera n c e i n d u c t o r an d ca p a ci t o r val u es. the cal i b r a t ion is typ i cal l y p e r f o r m e d on ce a t p o w e r - u p . the a d c con t ain s a six t h o r der m u l t ib i t b a nd- p a ss - ? m o d u - l a tor t h a t a c h i e v e s ve r y h i g h i n s t an t a ne ou s dy n a m i c r a nge ove r a n a r r ow f r e q u e nc y b a nd c e n t e r e d a t f cl k /8. t h e m o d u l a t o r o u t p ut is q u a d r a t u r e mixe d to b a s e b a nd an d f i l t er e d b y t h r e e cas c ade d li n e a r phas e fir f i l t ers t o r e m o ve o u t - o f -b and n o is e. t h e fi r s t f i r fi l t e r i s a fi x e d d e c i m a t e b y 1 2 u s i n g a f o u r t h o r d e r co m b f i l t er . th e s e co nd fir f i l t er als o us es a fo ur t h o r der co m b f i l t e r wi th p r ogra m m a b l e d e ci ma ti o n f r o m 1 t o 16. t h e thi r d fir s t a g e is p r og ra mma b l e fo r de cima t i o n o f e i t h er 4 o r 5. th e cas c ade d decima tio n f a c t o r is p r og ra mma b l e f r o m 48 t o 960. the de ci ma t i on f i l t er da t a is o u t p u t v i a t h e sy nchr o n o u s s e r i al in t e r f ace (ss i ) o f th e c h i p . a d di tio n al f u n c tio n ali t y b u il t in t o th e AD9864 in c l udes lo an d clo c k sy n t h e si ze rs, p r ogra mma ble a g c, an d a f l exi b le sy n c hr o - nou s s e r i a l i n t e r f a c e for output d a t a . the lo s y n t h e s i zer is a p r og ra mma b l e pll con s ist i n g o f a lo w n o is e phas e f r e q uen c y det e c t o r (p fd), a va r i a b l e o u t p ut c u r r en t cha r ge p u m p (c p), a 14-b i t r e fer e n c e divid e r , a a nd b co un ters, a nd a d u al mo d u l u s p r es caler . th e us er o n l y n e e d s t o add a n a p p r o p r i a t e lo op f i l t er a nd v c o fo r co m p let e o p era t ion. the c l o c k sy n t hesizer is e q u i val e n t t o t h e lo sy n t h e s i zer wi th t h e fol l o w in g dif f er en ces: ? i t do es n o t i n cl ude t h e p r es cale r o r a co un t e r . ? i t in c l udes a n e ga ti v e r e sis t an c e co r e us ed f o r v c o ge ne r a t i on. t h e a d 98 64 con t ains b o t h a var i ab l e g a i n am pl if ie r ( v g a ) and a di g i t a l v g a ( d v g a) . b o t h o f t h es e can op er a t e man u a l l y o r a u tom a t i ca l l y . i n man u a l mo de, t h e g a i n fo r e a ch is p r o g ram m e d th r o ug h t h e s p i. i n a u t o ma ti c ga in co n t r o l m o de , t h e ga in s a r e ad j u s t e d a u t o ma tical l y t o en s u r e th e ad c d o es n o t c l i p a n d tha t t h e r m s o u t p ut l e vel o f t h e a d c is e q ua l t o a p r o g rammab l e ref- er e n ce l e ve l. the v g a has 1 2 db o f a tte n u a t io n r a n g e and is im ple m e n te d b y ad j u s t ing t h e a d c f u l l -s cal e r e fer e n c e le ve l . th e d v ga gain i s im ple m e n t e d b y s c alin g t h e ou t p u t o f t h e de ci ma t i on f i l t er . th e d v ga is m o s t us ef u l in ext e n d in g t h e d y na mic ra n g e in na r - r o w-b a nd a p pli c a t ion s r e q u ir ing 16-b i t i and q d a t a fo r m a t . the ss i p r o v ide s a p r og ra mma b l e f r a m e s t r u c t ur e , al lo win g 24-b i t o r 16-b i t i a nd q da t a and f l exi b ili t y b y in c l udin g a t t e n u a t io n and rss i d a t a if r e quir e d . rev. 0 | page 3 of 4 4
AD9864 rev. 0 | page 4 of 4 4 AD9864 specifications table 1. vddi = vddf = vdda = vddc = vddl = vddh = 2.7 v to 3.6 v, vddq = vddp = 2.7 v to 5.5 v, f clk = 18 msps, f if = 109.65 mhz, f lo = 107.4 mhz, f ref = 16.8 mhz, unless otherwise noted. standard operating mode: vga at minimum attenuation setting, synthesizers in normal (not fast acquire) mode, deci mation factor = 900, 16-bit digita l output, and 10 pf load on ssi output pins. parameter temperature test level min typ max unit system dynamic performance 1 ssb noise figure @ minimum vga attenuation 2, 3 full iv 7.5 9.5 db @ maximum vga attenuation 2,3 full iv 13 db dynamic range with agc enabled 2,3 full iv 91 95 db if input clip point @ maximum vga attenuation 3 full iv C20 C19 dbm @ minimum vga attenuation 3 full iv C32 C31 dbm input third order intercept (iip3) full iv C12 C7.0 dbm gain variation over temperature full iv 0.7 2 db lna + mixer maximum rf and lo frequency range full iv 300 500 mhz lna input impedance 25c v 370||1.4 ? ||pf mixer lo input resistance 25c v 1 k ? lo synthesizer lo input frequency full iv 7.75 300 mhz lo input amplitude full iv 0.3 2.0 v p-p fref frequency (for sinusoidal input only) full iv 8 25 mhz fref input amplitude full iv 0.3 3 v p-p fref slew rate full iv 7.5 v/s minimum charge pump current @ 5 v 4 full vi 0.67 ma maximum charge pump current @ 5 v 4 full vi 5.3 ma charge pump output compliance 5 full vi 0.4 vddp C 0.4 v synthesizer resolution full iv 6.25 khz clock synthesizer clk input frequency full iv 13 26 mhz clk input amplitude full iv 0.3 vddc v p-p minimum charge pump output current 4 full vi 0.67 ma maximum charge pump output current 4 full vi 5.3 ma charge pump output compliance 5 full vi 0.4 vddq C 0.4 v synthesizer resolution full vi 2.2 khz -? adc resolution full iv 16 24 bits clock frequency (f clk ) full iv 13 26 mhz center frequency full v f clk /8 mhz pass-band gain variation full iv 1.0 db alias attenuation full iv 80 db gain control programmable gain step full v 16 db agc gain range full v 12 db gcp output resistance full iv 50 72.5 95 k ? 1 this includes 0.9 db loss of matching network. 2 agc with dvga enabled. 3 measured in 10 khz bandwidth. 4 programmable in 0.67 ma steps. 5 voltage span in which lo (or clk) charge pump output current is maintained within 5% of nominal value of vddp/2 (or vddq/2).
AD9864 rev. 0 | page 5 of 44 parameter temperature test level min typ max unit overall analog supply voltage (vdda, vddf, vddi) full vi 2.7 3.0 3.6 v digital supply voltage (vddd, vddc, vddl) full vi 2.7 3.0 3.6 v interface supply voltage (vddh) 1 full vi 1.8 3.6 v charge pump supply voltage (vddp, vddq) full vi 2.7 5.0 5.5 v total current operation mode 2 full vi 17 ma standby full vi 0.01 ma operating temperature range C40 +85 c 1 vddh must be less than vddd + 0.5 v. 2 clock vco off and additional 0.7 ma with vga @ maximum attenuation.
AD9864 rev. 0 | page 6 of 4 4 digital specifications table 2. vddi = vddf = vdda = vddc = vddl = vddh = 2.7 v to 3.6 v, vddq = vddp = 2.7 v to 5.5 v, f clk = 18 msps, f if = 109.65 mhz, f lo = 107.4 mhz, f ref = 16.8 mhz, unless otherwise noted. standard operating mode: vga at minimum attenuation setting, synthesizers in normal (not fast acquire) mode, deci mation factor = 900, 16-bit digita l output, and 10 pf load on ssi output pins. parameter temperature test level min typ max unit decimator decimation factor 1 full iv 48 960 pass-band width full v 50% f clkout pass-band gain variation full iv 1.2 db alias attenuation full iv 88 dbm spi-read operation (see figure 30) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock high (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pe to pc setup time (t s ) full iv 5 ns pc to pe hold time (t h ) full iv 5 ns spi-write operation 2 (see figure 29) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock high (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pc to pd (or doutb) data valid time (t dv ) full iv 3 ns pe to pd output valid to hi-z (t ez ) full iv 8 ns ssi 2 (see figure 32) clkout frequency full iv 0.867 26 mhz clkout period (t clk ) full iv 38.4 1153 ns clkout duty cycle (t hi , t low ) full iv 33 50 67 ns clkout to fs valid time (t v ) full iv C1 +1 ns clkout to dout data valid time (t dv ) full iv C1 +1 ns cmos logic inputs 3 logic 1 voltage (v ih ) full iv vddh C 0.2 v logic 0 voltage (v il ) full iv 0.5 v logic 1 current (i ih ) full iv 10 a logic 0 current (i il ) full iv 10 a input capacitance full iv 3 pf cmos logic outputs 2, 3, 4 logic 1 voltage (v oh ) full iv vddh C 0.2 v logic 0 voltage (v ol ) full iv 0.2 v 1 programmable in steps of 48 or 60. 2 cmos output mode with c load = 10 pf and drive strength = 7. 3 absolute maximum and minimum input/output levels are vddh + 0.3 v and C0.3 v. 4 i ol = 1 ma; specification is also de pendent on drive strength setting.
AD9864 absolute maximum ratings ta bl e 3 . a d 98 64 a b s o l u t e ma xi m u m r a ti ng s parameter with respect t o min max unit vddf, vdda, v ddc, vddd, vddh, v ddl, vddi gndf, gnda, g n dc, gndd, gndh, gnd l , g n di, gnds ? 0 . 3 + 4 . 0 v vddf, vdda, v ddc, vddd, vddh, v ddl, vddi vddr, vdd a , v ddc, vddd, vddh, v ddl, vddi ? 4 . 0 + 4 . 0 v vddp, vddq gndp, gndq ?0.3 +6.0 v gndf, gnda, g n dc, gndd, gndh, gnd l , g n di, gndq, gn dp, gnds gndf, gnda, g n dc, gndd, gndh, gnd l , g n di, gndq, gn dp, gnds ? 0 . 3 + 0 . 3 v mxop, mxon, lop, lon, ifin, cxif, cxvl, cxvm gndh ?0.3 vddi + 0.3 v pc, pd, pe, c l kout, douta, doutb, fs, syncb gndh ?0.3 vddh + 0.3 v if2n, if2p, gcp, gcn gndf ?0.3 vddf + 0.3 v vfefp, vr egn, rref gnda ?0.3 vdda + 0.3 v i o u t c g n d q ? 0 . 3 v d d q + 0 . 3 v ioutl gndp ?0.3 vddp + 0.3 v clkp, clkn gndc ?0.3 vddc + 0.3 v fref gndl ?0.3 vddl + 0.3 v junction tempe r ature 150 c storage temperature ?65 +150 c lead temperature 300 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y ca us e p e r m an e n t da ma g e t o t h e de vice . this is a s t r e s s ra t i n g o n ly ; f u nc t i on a l o p e r a t i o n of t h e d e v i c e a t t h e s e or a n y ot h e r c o n d i t i ons ab ove t h o s e i n d i c a te d i n t h e op e r a t i o n a l s e c t i o n of t h i s sp e c if ica t ion is not i m pl i e d. e x p o su re to ab s o lute m a x i m u m r a t i ng c o n d i t i ons for e x te nd e d p e r i o d s m a y af fe c t d e v i c e rel i a b i l it y . thermal resistance rev page of 4 4
AD9864 pin conf iguration and fu nctional descri ptions pin 1 identifier top view (not to scale) AD9864 1 mxop 36 gndl 2 mxon 35 fref 3 gndf 34 gnds 4 if2n 33 syncb 5 if2p 32 gndh 6 vddf 31 fs 7 gcp 30 doutb 8 gcn 29 douta 9 vdda 28 clkout 10 gnda 27 vddh 11 vrefp 26 vddd 12 v refn 25 pe 48 v ddi rre f 13 lon clkp 42 19 43 lop gndc 18 44 c xvl v ddc 17 45 gndi gndq 16 46 cx if ioutc 15 47 ifin v ddq 14 c xvm clkn 41 20 v ddl gnds 40 21 39 v ddp gndd 22 38 ioutl pc 23 37 gndp pd 24 04319-0-002 f i g u re 2. 48-l e ad l f csp , back s i de p a dd l e c o n t act i s c o nn e c t e d t o g r o u n d table 5. p i n f u n c t i on des c r i p t ion s ?48-l e ad lead fr ame c h i p scal e p a ck age (lf c sp ) pin no. mnemonic description 1 mxop mix e r output, p o sitive 2 mxon mix e r output, n e gative 3 gndf ground for front end of adc 4 if2n second if input (to adc), negati ve 5 if2p second if input (to adc), positive 6 vddf positive supply for front end of adc 7 g c p filter capacitor for adc full-scale control 8 gcn full-scal e contr o l ground 9 vdda positive supply for adc back end 10 gnda ground for adc back end 11 vrefp voltage reference, positive 12 vrefn voltage reference, negative 1 3 r r e f reference resist or: requires 100 k ? pin no. mnemonic description 27 vddh positive supply for digital interface 28 clkout clock output for ssi port 29 douta data output for ssi port 3 0 d o u t b data output for ssi port (inverte d) or spi port 31 fs frame sync for ssi port 32 gndh ground for digital interface 3 3 s y n c b resets ssi and decimatorcounters active low 3 4 g n d s substrate g r o u n d 3 5 f r e f reference frequ ency input for both synthesizers 36 gndl ground for lo s y nthesizer 3 7 g n d p ground for lo s y nthesizer charge pump 3 8 i o u t l lo synthesizer charge pump out current 3 9 v d d p positive supply for lo synthesizer charge pump 40 vddl postive supply for lo synthesizer 4 1 c x v m ex ternal filter capacitor dc ou tput of lna 4 2 l o n lo input to mix e r and lo synthesizer, negative 4 3 l o p lo input to mix e r and lo synthesizer, positive 4 4 c x v l external bypass capacitor for ln a power supply 45 gndi ground for mixer and lna 4 6 c x i f external capacit o r for mixer v-i converter bia s 47 ifin first if input (to lna) 48 vddi positive supply for lna and mix e r rev. 0 page 8 of 4 4
AD9864 rev. 0 | page 9 of 4 4 defi ni tio n of s p ecific atio ns/tes t meth ods single sideband noise fig u re (ssb nf) no ise fi gur e (n f ) is defi ne d as the degr a d a t io n in s n r per - formance ( i n d b ) of an if inpu t sign al af ter it passes t h rough a compone n t or system. it c a n be expressed w i t h the equ a t i on ( ) / log 10 = th e ter m ss b is applica b le fo r h e ter o dy ne sy ste m s co nt ai ni ng a mixer. it indic a tes that the desir e d sig n al spectr um resides o n on ly on e sid e of th e lo frequenc y (i.e., single sideband); t h us a noisel e ss mix e r has a nois e figure of 3 db. the ssb noise fig u re of the ad 98 64 is determ ined by the equati on ( ) [] C dbm/hz 174 ( C log 10 C ? = where p in is the in put power of an un mo d u lated carrier, bw is the noise measu r ement bandwidth, C174 db m / h z is th e th er- mal noise floor at 293k, and snr is the measur ed sig n al-to- noise ratio in db of the ad986 4. no te t h a t p in is set to C85 dbm to mi ni mi ze a n y degradat ion i n measured s n r due to phase no is e from t h e rf and lo s i gnal gener a to r s . t h e if fr equency , clk fr equency , a nd deci m a tio n factors are selec t ed to mi ni mi ze any spurious c o mpone n ts falli ng wi th in th e me asure m ent ba nd wi dth . not e also th at a ba nd wi dth of 1 0 khz is use d for the d a t a sh eet specific atio n. al l referen c es to n o ise figures within th is dat a sh ee t imply si ngl e side ba n d no is e figur e . inp u t thir d or de r int e r c e p t ( iip3) iip3 is a figure of merit use d to deter m i n e a compone n t s or systems suscep tibility to in term od ulatio n distortion (imd) fr o m its t h ir d o r der no nl in ear i t i es. two un mo dula ted c a r r i er s at a sp ecifi e d fr equency rela tio n sh ip ( f 1 and f 2 ) are inject ed into a no nl in ear sy st em ex h i b i ti ng t h ir d o r d e r no nl ine a r i t i es pr o - duci ng imd co mpo n e n ts at 2 f 1 C f 2 and 2 f 2 C f 1. iip3 graphi- cally represent s the extr apolate d i n tersec tion o f the carri ers input pow e r wi t h th e th ird orde r imd component whe n plot- ted in db. t h e d i ffer e nce in po w e r ( d in dbc) be twee n t h e t w o car r i er s a nd t h e r e sulti n g th ir d o r der imd co m p o n ent s ca n be deter m i n e d from th e equa tio n () C 3 2 = d y na m i c ra nge (d r) dy nami c r a ng e is t h e me asur e o f a s m al l tar g e t i n p u t s i g n al ( p targ et ) i n t h e pres e n c e of a l a r g e u n w a nte d i n t e rfe r er s i g n al ( p int e r ). t y p i ca l l y, the la rg e si gna l wi ll cau s e s o me unwan t ed ch ar ac te ri st ic of th e co mpo n e n t or sys t e m to de g r a d e , t h us mak - in g it unab le t o de te ct t h e sma l le r t a rge t si gna l corre ct l y . in th e case of the ad9 864, it is of ten a degr adatio n in no is e f i g u r e at in crea se d vga a tten u a t i o n se ttin g s th at limit s its d y n a mi c ran g e. the t e s t me thod for the a d 98 64 is as f o llo w s . the s m all t a rg et s i gn al (an unm o d u la ted ca rrie r) i s in put a t the cent e r of th e if fre q uen c y, and it s powe r l eve l ( p targ e t ) i s adjus t e d to ac hi ev e an snr ta rg e t of 6 db . the p o we r of t h e si gna l is t h en in c r ea sed b y 3 db prior to i n jec t i n g the i n ter f erer s i g n al . the offs et fre q u e ncy of t h e int e rf ere r sig n al is s e l e ct e d so t h at aliase s p r odu c e d by t h e d e cim a ti on fi lter s res p on se a s w e l l as pha s e n o i s e f r om the l o ( d ue t o re ci p r oca l mi xin g ) d o not fa ll ba ck wi thin t h e mea s u r e- men t bandw idth . for th is rea s on , an off s et of 110 khz was s e le cted . the in te rfere r si gna l (a ls o an unm o du lat e d ca rrie r ) is t h en inj e cted into th e i n put and it s powe r l eve l is in crea se d t o the point ( p in t e r ) w h e r e t h e t a r g e t s i gnal s n r is re duce d to 6 db . the dy nami c r a ng e i s de te r m i n e d w i th t h e equ a t i o n target target inter snr p p dr + = C note that the AD9864s ag c is enabled for this test. if input clip point th e if input cl i p point is def i ned as the inpu t power tha t results in a dig i tal output le vel 2 db belo w full-s c ale. unlike other li near co mpone n ts t h at t y pically exhi bit a soft compres- sion (character ized by its 1 db c o mpression point), an a d c exhibits a hard compression o n ce its input s i gnal excee d s its rated maximu m input s i gnal range. i n the case of the AD9864, whic h co nt ai ns a - ? a d c, har d co mpr e ss io n sho u ld b e avo i ded bec a us e it cau s es se ver e snr degr a d a t io n.
AD9864 typical perf orm ance cha r acte ristics dd nf b 9 6 6 8c c 4 c 6 8 8 9 49 f i gue ssb n ise f i gue s su y dd dr b 98 6 9 9 96 9 94 9 4 c 8c c 49 f i gue 4 d y nmi rnge s su y dd input clip point bm 9 6 8 c c 4 c 49 f i g u e m i n i m u m g a at tenut i n c i p i n t s su y dd iip bm 6 8 c c 4 c 8 6 4 494 fi g u e 6 i i p s s u y dd input clip point bm 6 4 c 8c c 8 8 9 9 496 f i g u e m i m u m g a at tenut i n c i p i n t s su y lo drie bm gain ariation b 4 8 4 6 8 498 f i g u e 8 n m ize g in i t in s l o d ie d d rev. 0 | page 10 of 44
AD9864 lo drive (dbm) nois e figure (dbc) 9.0 20 10 0 5 8.6 8.2 7.8 7.4 7.0 8.4 8.0 7.6 7.2 5 15 nf imd 8.8 i m d wi th i f i n = 36 dbm (dbc) 0 2 0 4 0 6 0 8 0 3 0 5 0 7 0 1 0 04319- 0- 009 f i g u re 9. n o is e f i g u r e and im d v s . l o d r ive ( v ddx = 3. 0 v ) ifin (dbm) dbfs 0 30 14 adc does not go into hard compression 28 26 24 22 20 18 1 4 2 4 6 8 10 12 2.7v 3.0v 3.3v 3.6v 16 04319-0-011 f i g u re 10. g a in co mpr e ssion v s . ifin channel bandwidth (khz) nois e figure (db) 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit i/q data 16-bit i/q data 16-bit i/q data with dvga enabled 04319-0-013 f i gure 11. no ise f i g u r e v s . b w (m in i m u m atten u ati o n, f clk = 1 3 ms ps) ifin (dbm) dbm 12 36 33 3 0 27 2 4 21 1 8 15 12 9 6 3 0 1 8 24 3 0 36 1 5 21 27 3 3 04319-0-010 f i g u re 12. g a in co mpres s i on v s . ifin wit h 16 d b lna at t e nuat or e n abl e d ifin (dbm) imd (dbm) 55 109 61 67 73 85 91 103 51 48 45 42 39 36 33 30 pin 2.7v 3.0v 3.6v 3.3v 115 97 79 pin (dbfs) 1 5 4 2 1 8 2 1 2 4 3 0 3 3 3 9 4 5 3 6 2 7 04319- 0- 012 f i g u re 13. imd v s . ifin channel bandwidth (khz) nois e figure (db) 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data with dvga enabled 04319-0-014 16-bit data f i gure 14. no ise f i g u r e v s . b w (m in i m u m atten u ati o n, f clk = 1 8 ms ps) rev. 0 | page 11 of 44
AD9864 channel bandwidth (khz) nois e figure (db) 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data 16-bit data with dvga enabled 04319-0-015 fi g u r e 1 5 . n o i s e fi g u r e v s . b w ( m i n i m u m a t t e n u a t i o n , f clk = 2 6 ms ps) vga attenuation (db) nois e figure (db) 14 0 7 12 69 3 13 12 11 10 9 8 bw = 15khz (k = 0, m = 9) bw = 75khz (k = 0, m = 1) bw = 50khz (k = 0, m = 2) 04319-0-017 fi g u r e 1 6 . n o i s e fi g u r e v s . v g a a t t e n u a t i o n ( f clk = 1 8 ms ps) ifin (db) imd (db) 45 130 30 40 50 60 70 80 90 100 110 120 4 2 39 36 33 3 0 27 24 pin po ut (dbfs) 5 30 10 15 20 25 40 35 45 04319- 0- 019 f i g u re 17. imd v s . ifin (f clk = 13 msps) vga attenuation (db) nois e figure (db) 11.5 0 7.0 12 6 9 3 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 bw = 6.78khz (k = 0, m = 15) bw = 12.04khz (k = 0, m = 8) bw = 27.08khz (k = 0, m = 3) 04319-0-016 fi g u r e 1 8 . n o i s e fi g u r e v s . v g a a t t e n u a t i o n ( f clk = 1 3 ms ps) vga attenuation (db) nois e figure (db) 14 0 7 12 6 9 3 13 12 11 10 9 8 bw = 27.08khz (k = 1, m = 9) bw = 90.28khz (k = 1, m = 2) bw = 135.42khz (k = 1, m = 1) 04319-0-018 fi g u r e 1 9 . n o i s e fi g u r e v s . v g a a t t e n u a t i o n ( f clk = 2 6 ms ps) ifin (dbm) imd (dbm ) 45 130 30 40 50 60 70 80 90 100 110 120 42 39 36 33 30 27 2 4 pin pin (dbfs) 5 30 10 15 20 25 40 35 45 04319-0-020 f i g u re 20. imd v s . ifin (f clk = 18 msps) rev. 0 | page 12 of 44
AD9864 rev. 0 | page 13 of 44 ifin (dbm) imd (dbc) 4 5 130 30 40 50 60 70 80 90 100 110 120 42 39 36 33 3 0 27 24 pin pin (dbfs) 5 30 10 15 20 25 40 35 45 04319-0-021 f i g u re 21. imd v s . ifin (f clk = 26 msps) frequency (mhz) nois e figure (db) 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 04319-0-023 16-bit with dvga 24-bit fi g u r e 2 2 . n o i s e fi g u r e v s . f r e q u e n c y ( m ini m u m at tenuat io n, f clk = 2 6 ms p s , bw = 10 kh z) frequency (mhz) iip3 ( d bm) 0 0 10 2 4 6 8 50 500 100 150 200 250 300 350 400 450 04319-0-023 f i gure 23. input ii p3 vs. f r eq uenc y (f cl k = 2 6 ms ps) frequency (mhz) nois e figure (db) 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit with dvga 04319-0-022 fi g u r e 2 4 . n o i s e fi g u r e v s . f r e q u e n c y ( m ini m u m at t e nua t ion, f clk = 18 msps , bw = 10 kh z) frequency (mhz) iip3 ( d bm) 0 0 2 4 6 8 10 50 500 100 150 200 250 300 350 400 450 04319-0-025 f i gure 25. input ii p3 vs. f r eq uenc y (f cl k = 1 8 ms ps) interferer level (dbm) noise figure (dbc) 20.0 55 8.0 18.5 15.5 12.5 11.0 9.5 5 1 0 noise figure agc 17.0 14.0 15 20 25 30 35 4 0 45 50 mean agc attn value 128 0 112 80 48 32 16 96 64 04319- 0- 026 f i g u re 26. no is e f i g u r e v s . int e r f e r e r l e vel (1 6-bit d a t a , bw = 1 2 . 5 kh z, a g cr = 1, f in t e r f e r er = f if + 1 1 0 kh z)
AD9864 interferer leel bm nois e figure b 6 8 9 noise figure agc attn 4 4 4 me an agc attn a lue 6 4 6 96 64 9 8 49 f i gure 2 7 . noi s e f i g u r e vs . inter f er er l e v e l (16 - bi t d a ta wi t h dvg a , bw = 1 2 . 5 kh z, a g cr = 1, f in t e r f e r er = f if + 1 1 0 kh z) interferer level (dbm) nois e figure (dbc ) 16 65 8 15 13 11 10 9 5 15 noise figure agc attn 14 12 2 5 3 5 45 5 5 me an agc attn v a lue 128 0 32 96 64 04319-0-028 f i g u re 28. no is e f i g u r e v s . int e r f e r e r l e vel (2 4-bit d a t a , bw = 1 2 . 5 kh z, a g cr = 1, f in t e r f e r er = f if + 1 1 0 kh z) rev. 0 page 14 of 44
AD9864 rev. 0 | page 15 of 44 serial peripheral interface (spi) the spi is a bidirectional serial port. it is used to load the configuration information into the registers listed below as well as to read back their contents. table 6 provides a list of the registers that can be programmed through the spi port. addresses and default val ues are given in hexadecimal form. table 6. spi address map address (hex) bit breakdown width default value name description power control registers 0x00 (7:0) 8 0xff stby standby control bits (ref, lo, ck o, ck, gc, lnamx, unused, and adc). default is power-up condition of standby. 0x01 (3:2) 2 0x00 ckob ck oscillator bias (0 = 0.25 ma, 1 = 0.35 ma, 2 = 0.40 ma, 3 = 0.65 ma). (1:0) 2 0x00 adcb do not use. 0x02 (7:0) 8 0x00 test factor y test mode. do not use. agc 0x03 (7) 1 0 atten apply 16 db at tenuation in the front end. (6:0) 7 0x00 agcg (14:8) agc attenuation se tting (7 msbs of a 15-bit unsigned word). 0x04 (7:0) 8 0x00 agcg (7:0) agc attenuation se tting (8 lsbs of a 15-bit unsigned word). 0x05 (7:4) 4 0x00 agca agc attack bandwidth setting. default yields 50 hz loop bandwidth. (3:0) 4 0x00 agcd agc decay time setting . default is decay time = attack time. 0x06 (7) 1 0 agcv enable digital vg a to increase agc range by 12 db. (6:4) 3 0x00 agco agc overload update setting. default is slowest update. (3) 1 0 agcf fast agc (minimizes resistance seen between gcp and gcn). (2:0) 3 0x00 agcr agc enable/reference level (disabled, 3 db, 6 db, 9 db, 12 db, 15 db below clip). decimation factor 0x07 (7:5) 3 unused (4) 1 0 k decimation factor = 60 ( m + 1), if k = 0; 48 ( m + 1), if k = 1. (3:0) 4 0x04 m defaul t is decimate-by-300. lo synthesizer 0x08 (5:0) 6 0x00 lor (13:8) reference frequency divider (6 msbs of a 14-bit word). 0x09 (7:0) 8 0x38 lor (7:0) reference frequency divisor (8 lsbs of a 14-bit word). default (56) yields 300 khz from f ref = 16.8 mhz. 0x0a (7:5) 3 0x05 loa a counter (prescaler control counter). (4:0) 5 0x00 lob (12:8) b counter msb (5 msb of a 13-bit word). default loa and lob values yi eld 300 khz from 73.35 mhz to 2.25 mhz. 0x0b (7:0) 8 0x1d lob (7:0) b counter lsb (8 lsb of a 13-bit word). 0x0c (6) 1 0 lof enable fast acquire. (5) 1 0 loinv invert charge pump (0 = source current to increase vco frequency). (4:2) 3 0x00 loi charge pump current in normal operation. i pump = (loi +1) 0.625 ma. (1:0) 2 0x03 lotm manual control of lo charge pump (0 = off, 1 = up, 2 = down, and 3 = normal). 0x0d (5:0) 6 0x00 lofa (13:8) lo fast acqu ire time unit (6 msbs of a 14-bit word). 0x0e (7:0) 8 0x04 lofa (7:0) lo fast acquir e time unit (8 lsbs of a 14-bit word). clock synthesizer 0x10 (5:0) 6 0x00 ckr (13:8) reference freque ncy divisor (6 msbs of a 14-bit word). 0x11 (7:0) 8 0x38 ckr (7:0) reference frequency divisor (8 lsbs of a 14-bit word). default yields 300 khz from f ref = 16.8 mhz; minimum = 3, maximum = 16383. 0x12 (4:0) 5 0x00 ckn (12:8) synthesized frequency divisor (5 msbs of a 13-bit word).
AD9864 rev. 0 | page 16 of 44 address (hex) bit breakdown width default value name description 0x13 (7:0) 8 0x3c ckn (7:0) synthesized frequency divisor (8 lsbs of a 13-bit word). default yields 300 khz from 18 mhz; minimum = 3, maximum = 8191. 0x14 (6) 1 0 ckf enable fast acquire. (5) 1 0 ckinv invert charge pump (0 = source current to increase vco frequency). (4:2) 3 0x00 cki charge pump current in normal operation. i pump = (cki + 1) 0.625 ma. (1:0) 2 0x03 cktm manual control of clk charge pump (0 = off, 1 = up, 2 = down, and 3 = normal). 0x15 (5:0) 6 0x00 ckfa (13:8) ck fast acquire time unit (6 lsbs of a 14-bit word). 0x16 (7:0) 8 0x04 ckfa (7:0) ck fast acquir e time unit (8 lsbs of a 14-bit word). ssi control 0x18 (7:0) 8 0x12 ssicra ssi control register a. see tabl e 8. default is fs and clkout three-stated. 0x19 (7:0) 8 0x07 ssicrb ssi control register b. see table 8 (16-bit data, maximum drive strength). 0x1a (3:0) 4 0x01 ssiord output rate divisor. f clkout = f clk /ssiord. adc tuning 0x1c (1) 1 0 tune_lc perform tuning on lc por tion of the adc (cleared when done). (0) 1 0 tune_rc perform tuning on rc por tion of the adc (cleared when done). 0x1d (3:0) 3 0x00 capl1 (2:0) coarse capacitance setting of lc tank (lsb is 25 pf, differential). 0x1e (5:0) 6 0x00 capl0 (5:0) fine capacitance setti ng of lc tank (lsb is 0.4 pf, differential). 0x1f (7:0) 8 0x00 capr capacitance setting for rc resonator (64 lsb of fixed capacitance). test registers and spi port read enable 0x37C0x39 (7:0) 8 0x00 test fact ory test mode. do not use. 0x3a (7:4) 4 0x00 test factor y test mode. do not use. (3) 1 0 spiren enable read from spi port. (2:0) 3 0x00 test factory test mode. do not use. 0x3b (7:4) 4 0x00 test factor y test mode. do not use. (3) 1 0 tri three-state doutb. (2:0) 3 0x00 test factory test mode. do not use. 0x3cC0x3e (7:0) 8 0x00 test fact ory test mode. do not use. 0x3f (7:0) 8 subject to change id revision id (read-only); a write of 0x99 to this register is equivalent to a power-on reset.
AD9864 re pge 44 theory of operation serial port interface s pi te sei t te AD9864 s ie 4ie spi bi ity ing e i te ess t egistes tt nig ue te e ies inten metes t e eut ie sei mmu ni ti n t nsis ts pc eie enb e pe n b i i eti n t pd si gn t e in uts t pc pe n pd nt i n s mitt t igge i t nmin y steesis 4 entee b ut te ig i t inte e suy ie ddh a 4 i e spi i n t e e n be en be by se tti ng te msb t e ssicrb egis t e reg 9 bit n s e tting reg a t esuti n g i n t e utut t e i n g n t e d o utb i n nte t t si ne te eu t e u st t e set s dou t b bus nte n tin is ssib e systems s ing te spi utu t ine t i n y bus nt en ti n t e do utb in n b e tee st t e by setti ng t e ut nt bi t i n te t ee st t e bit re g b bit tis bit n t e n be tgg e t g in es s t te s e sp i utut ine a n 8b i t i n stut i n e e must m n y e e n i t e spi eti n ony te it e e ti n su ts n u t i n e me nt m e i s t e ent i e i t b e nigue i n si nge ite eti n t e instut in e e is s n in t b e it i n u es e n t ite in i t bit s i ess bits n dn t ce b i t t e t b i ts i m me i tey t e i n st u t i n e e b t e n i t e etins nt e t t t e e ss n t e y s gie n m s b ist tbe in st u t i n hee in m t i n m s b l s b i i 6 i i 4 i i i i r a a 4 a a a a x f i gu e 9 i u s t t e s t e t i min g e u i em e n ts i t e e t i n t t e s p i t a t e t e e i e enb e p e sig n g es t p d e t i nin g t t e in s t u t i n e e is e n t e i sin g e g e s t e pc t ini t i t e i t e e t i n t e e n t i t e b i t is s e t a t e t e i n s t u t i n e e is e t e e i g t t b i ts e t i ni n g t t e s e i ie e g i s t e e s i t e in t t e t i n pd n t e i si n g e ge s t e n e t eigt yes pe stys u i n g t e e ti n n g es ig t te en te t n se i pe ises bee te e i g t yes e ss e t e eti n is bte i pe stys n it i n ei gt y es te est in t in ess is i n em en t e n n t e ei g t b i t s t e s i te in agin s u p e ise ey t e u e nt by te is i g n e by using t is i m i it es si ng m e te i n b e nigu e it s i ng e ite et in r e gistes ient i ie s be ing su b et t euent utes nme y tse ssit e i t e nt n ag c e ti n e be en ssig n e e nt esses t mi ni mi ze t e t i me euie t u t e t em nte tt mu t i b yte egistes e b i g enin t e m st sig n ii nt byte s te e ess n e ute en ite t t e est s i gnii nt byte us f i gu e iust tes t e t i mi ng e et in t t e spi t atug te AD9864 es nt euie e ess e etin it is te n us eu i n t e ut e e m en t s e syst e m u t e n t i ti n n te t t t e e b en b e bit r egi s te a bit must b e set e e tin it ie spi inte e ate te ei e e n be pe sign g e s t pd e t i ni ng t t e ins t u ti n ee is e n te isi ng e g e s te p c a e etin u s i te e nt it e i n i t is set ig ate t e es s bits t e i n stut i n e e e e t e eig t t bi ts e ti ni ng t t e seiie egi ste e sit e ut t e t in p d n te i n g e ges te n e t eigt yes i te 4 ie spi i n t e e is e n b e te eig t t b i ts i s e n te do utb in i t t e s me t i m i ng e tins i s ts e e ing t p d ate t e st t b i t is s i te ut t e use s u e tun pe ig using p d t beme teestte n etun t its nm sttus s n inut in s i ne te u t in e me nt m e is n t su te e etins n i n stuti n e e is euie e egi ste e e t in n pe mus t et u n ig bee in ititin g te n e t e etin pe pc pd t h t ds t hi t s t dh t lo t cl r a a4 a d d6 d d dont care 499 f i g u re 29. spi wr ite oper ation timin g
AD9864 rev. 0 | page 18 of 44 t pe pc pd dont care dont care dont care dont care dont care dont care dont care doutb d1 d0 d6 d7 d1 d0 d6 d7 r/w a5 a1 a0 t s t hi t low t ds t dh t dv t ez t clk 04319-0-030 f i g u re 30. spi read operation timin g synchr onous serial interface (ssi) the AD9864 p r o v ides a hig h deg r ee o f p r og ra m m a b il i t y o f i t s ss i o u t p u t da ta fo r m a t , co n t r o l sig n als, a n d t i min g p a ram e t e rs t o acco m m o d a t e va r i o u s dig i t a l in t e r f aces. i n a 3-w i r e dig i t a l in t e r f ace , t h e AD9864 p r o v ides a f r a m e s y n c sig n al (fs), a c l o c k o u t p u t (clk o u t ) , an d a ser i a l da ta s t r e a m (d o u t a ) signal to t h e h o st d e vice. i n a 2 - wir e i n t e r f ace, t h e f r am e s y n c i n fo r m a - tio n is em bedde d in t o the da t a str e a m , th us o n l y clk o ut and d o u t a ou t p u t sig n als a r e p r o v ide d t o t h e h o s t de vice . the ss i co n t r o l r e g i s t ers a r e ss i c ra, ss i c rb , and ss i o rd . t a b l e 8 shows the differ e nt bit fields as s o ciate d w i th th e s e regist ers. the primary output of the ad 9 864 is the converted i and q de modul a te d si gnal av aila ble fr om the s s i port as a seri al b i t strea m cont ai ne d wi th in a fram e. t h e output fr ame r a te is equa l to the modul a to r clock frequenc y (f clk ) divid e d by the dig i tal filters deci ma ti on factor th at is programme d i n th e dec i mato r regis t er (0x07). the bi t stream consists of an i word followed by a q word, w h ere e a ch wor d is eit h er 24 b i ts or 16 bits long an d is g i ve n ms b fir s t in two s com p lement form . two optional bytes may also be i n cluded wit h i n the ssi frame followi ng t h e q wo r d . on e by te co nt ai ns t h e agc a tte nua t io n a nd t h e o t her byte cont ai ns b o th a count of mo dul a to r r e set even ts a nd an esti mate of the receive d sig n al ampl itu d e (relat ive to full scale of the AD9864 s adc). f i gur e 3 1 illustrates the structure of the ssi data frames in a nu mber of ssi modes . th e two optio n al bytes are out p ut if th e eag c bit of ssic r a is set. the firs t byt e conta i ns th e 8-bi t at tenu at ion setti ng (0 = no atte nu atio n, 25 5 = 24 db o f att e nua t io n), wh il e the s e co n d by t e co nta i ns a 2-b i t r e set fiel d a n d 6-bi t r e ceiv ed s i g n al str e ng th field. th e r e set f i eld co nta i n s th e nu mber o f mo dula to r r e set events si nce t h e last report, satu rati ng at 3. the receive d sig n al str e ngt h (rssi) field is a l i ne ar esti ma te o f the sign al str e ngt h at the output of t h e first dec i mat i on stag e; 60 corresponds to a full-scale s i gn al. th e two optio n al bytes follow t h e i a nd q da ta as a 16- bit word provide d th at t h e a a gc b i t of ssicra is not set. if th e aa g c bit is set, the tw o bytes follow t h e i a nd q da ta in a n alternat ing fashio n. in th is alter n at e agc dat a mo de, t h e lsb o f the by t e co nta i n i ng t h e agc a tte nua t io n is a 0, wh ile t h e lsb o f th e by te co nt ai ni ng r e set a nd rssi info r m atio n is a l way s a 1. in a 2- wire int e rface, the embe dde d fr a m e sy n c bit (ef s ) wit h in the ssic r a reg i ster is s e t to 1. in th is mode, t h e frami n g inform atio n is e m be d d ed in the dat a stre am, wi th e a ch e i gh t bits of d a t a surrounde d by a s t a r t bit (low) a n d a stop bi t (hig h) , and eac h frame ends wi th at le ast 10 hig h b i ts. fs remai n s eit h er low or three-st ate d (def au lt), depe nding on the s t ate of the sfs t bi t. ot her control bi ts can b e use d to i n vert t h e fra m e sync (sfsi), to delay t h e frame sync pulse by one clock perio d (slfs), to inver t the cloc k (sc k i), or to three- state th e clock (sckt). note t h at if efs is set, slfs is a do nt care. 24-bit i and q, eagc = 0, aagc = x:48 data bits 24-bit i and q, eagc = 1, aagc = 0:64 data bits 16-bit i and q, eagc = 0, aagc = x:32 data bits 16-bit i and q, eagc = 0, aagc = 0:32 data bits 16-bit i and q, eagc = 1, aagc = 1:40 data bits reset count reset count i(15:0) q(15:0) q(15:0) i(15:0) attn(7:1) q(15:0) i(15:0) q(15:0) i(15:0) q(23:0) i(23:0) q(23:0) i(23:0) attn(7:0) attn(7:0) ssi(5:1) ssi(5:0) ssi(5:0) 1 0 04319-0-031 f i g u re 31. ssi fr ame str u ctur e t h e ss io rd re gi st er co ntro ls t h e ou tp ut b i t r a t e (f cl k o u t ) of the s e ria l bit st re am. f clkou t c a n b e se t equ a l to t h e modu l a tor clo c k freq uency (f cl k ) or an int e ger fracti on of it . it i s equal t o f clk di vided b y the contents of th e s s io rd r e g i s t er. no te that f cl k o u t sho u l d be c h o s e n suc h t h at it do es no t intro d uc e har m f u l spu r s wi thin th e pa s s ban d of th e ta rge t si gna l . u s e r s m u s t ve ri fy tha t th e o u t p u t b i t ra te i s s u ff ic i e nt to ac co mmo d at e t h e re qu ir ed n u mbe r of bit s p e r frame for a se le ct ed w o rd size and d e c i mati on fa ct or. id le (hi g h ) bi ts a r e us ed to fill out ea ch fram e.
AD9864 table 8. ssi co ntrol re gisters n a m e i d t h defau l t descriptio n ssicra (addr = 0x18) aagc eagc efs sfst sfsi slfs sckt scki aagc 1 0 alternate agc data bytes. eagc 1 0 embed agc dat a . efs 1 0 embed frame sync. sfst 1 1 three-state frame sync. sfsi 1 0 invert frame sync. slfs 1 0 late frame sync (1 = late, 0 = ea rly). s c k t 1 1 three-state c l k o t . s c k i 1 0 invert c l k o t . ssicrb (add r = 0x19) 4spi d ds2 ds1 ds0 4spi 1 0 enable 4-ire s p i interface for spi read operation via dotb. d 1 0 i/q data-ord idth (0 = 16 bit, 1 bit24 bit). a utomatically 16-bit when the agcv = 1). ds 3 7 fs, clkot, and dot drive strength. ssiord (add r = 0x1a) div3 div2 div1 div0 div 4 1 output bit rate divisor f clk o t = f clk /ssiord. rev. 0 page 19 of 44
AD9864 rev. 0 | page 20 of 44 clkout fs dout clkout fs dout clkout fs dout clkout fs dout i15 i0 q15 q14 q0 i15 i0 q15 q14 q0 i15 i0 q15 q14 q0 attn7 atten6 rssi0 i15 q15 i8 stop bit start bit i7 i0 stop bit start bit scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 0 scki = 0, sckt = 0, slfs = 1, sfsi = 0, efs = 0, sfst = 0, eagc = 0 scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 1, aagc scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 1, eagc = 0 scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 0, eagc = 0; as above, but fs is low idle (high) bits hi-z 04319-0-032 f i gure 32. ssi t i min g for s e ver a l ssi cr a setti ngs wi th 16 - b i t i/ q da t a
AD9864 rev. 0 | page 21 of 44 table 9. n u mber of bits per fr ame for differen t ssicr settings dw eagc efs aagc number of bits per frame 0 (16 bit) 0 0 na 32 0 1 n a 4 9 * 1 0 0 4 8 1 0 1 4 0 1 1 0 6 9 * 1 1 1 5 9 * 1 (24 bit) 0 0 na 48 0 1 n a 6 9 * 1 0 0 6 4 1 0 1 5 6 1 1 0 8 9 * 1 1 1 7 9 * *th e n u m b er o f bi t s per f r a m e wi t h e m bedde d fra m e sy n c (ef s = 1 ) ; a s sum e a t lea s t 10 i d l e bi t s a r e d e si re d. the max i m u m ss i o rd s e t t i n g ca n b e deter m i n e d b y t h e eq ua ti o n ( ) ( ) [ ] frame per bits of no. factor decimation trunc ssiord / (1) w h er e tr unc is th e tr un ca t e d in t e g e r v a l u e . t a b l e 9 l i sts t h e n u m b er o f b i ts w i t h in a f r ame fo r 16 - b i t and 2 4 - b i t out p u t da t a fo r m a t s fo r al l o f t h e dif f eren t ssicr s e t t in g s . the dec i ma tion f a c t o r is deter m ine d b y t h e con t en ts o f reg i s t er 0x 07 . a n e x am pl e he lp s i l l u st r a te how t h e max i m u m s s i o r d s e t t i n g is det e r m in e d . s u p p o s e a us er s e lec t s a decima t i o n fac t o r o f 600 (reg ist e r 0x07, k = 0, m = 9) a nd p r ef ers a 3-wir e in ter f ace wi t h a de d i c a te d f r a m e sy n c (ef s = 0) co n t a i n i n g 2 4 -b i t da t a (d w = 1) wi t h n o na lter na t i n g em b e dde d a g c d a t a i n cl ude d (ea g c = 1, aa gc = 0). ref e r r i n g t o t a b l e 9, each frame will consist of 64 da ta b i ts. usi n g e q uatio n 1, th e maxi mu m ssiord setting is 9 (= trunc (600/64)). thus , the us er can select any ssio r d setting be tween 1 and 9. fi g u r e 3 2 illustr a tes t h e outpu t timing of the ss i port for several ssi cont rol register settings with 16-bit i/ q data, while f i gu r e 33 s h o w s t h e a s s o c i a t e d ti mi ng par a me ters. note t h at the s a me timing relat i ons h ip hol d s for 24-bi t i/q dat a , w i th t h e excep- tio n t h a t i a nd q wo r d leng ths no w beco me 24 bits. i n t h e defaul t mo de o f o p er atio n, da ta is shif te d o u t o n r i si ng e d ges o f clko ut after a pulse equ a l to a clock period i s output from the fr a m e sy nc ( f s) pin. as desc r i bed abo v e, t h e o u tput da ta consists of a 16 -bit or 24-bit i sample followe d by a 16-bit or 24-bit q s a mple , plus two o p tio n al by tes co nt ai ni ng ag c a nd status inform at i o n. i1 5 i 1 4 t clk t hi t v t dv t low cl ko ut fs do ut 04319-0-033 f i gure 33. ssi t i min g pa ra met e rs fo r s s i ti mi ng timing parameter s als o appl y to inve rted c l kout or fs mod e s , with t dv rela t i ve t o t h e fa l l i n g e d ge of t h e clk a n d/or f s . the AD9864 als o provides the means for contr o lling the switc h ing characteristics of the di g i tal outpu t si gnals vi a th e ds (drive stre ngt h ) field of the ssi crb. this featu r e is useful i n lim i ti ng sw itc h i n g tr a n si ent s a n d no is e fr o m th e dig i t a l o u tput tha t may ulti ma tely couple bac k into t h e analog signal pat h , potent ially d e gr ad ing t h e ad98 64s sens it ivi t y performance. f i gur e 34 and f i gur e 35 show how the nf can vary as a fu nc- tion of the ssi s e tting for an if frequency of 109.65 mhz. the followin g two observations can be made from t h ese fi gures: 1. th e nf b e co me s mo re sen s it ive to the ssi o u tp ut driv e strength le vel at hig h er sig n al bandwidth se ttings. 2. th e nf is depe nde nt o n th e nu mber o f bi ts w i t h i n a n ssi frame t h at beco me more sens it i v e to the ssi output dri ve strengt h le vel as the number of bits is i n creas e d. as a result , one shoul d sele ct the lo west po ssible ssi driv e strength se t- t i n g t h a t sti ll me e t s th e ssi ti min g re qui r em en ts. ssi output drive strength setting 2 10.0 4 no i se f i g ure (d b) 9.6 3 1 8.0 7 6 5 24-bit i/o data 9.8 9.4 9.2 9.0 8.6 8.8 8.4 8.2 16-bit i/0 data w/ dvga enabled 16-bit i/o data 04319-0-034 f i gure 34. nf vs. ss i output dr ive str e ngth (vddx = 3.0 v, f clk = 1 8 ms ps, bw = 1 0 kh z)
AD9864 ssi output drie strength setting 4 4 no i se f i g ure b 6 4bit io data 9 8 6bit io data dga enabled 6bit io data 49 f i gue nf s ss i outut d ie st e ngt dd f cl 8 ms ps b h z t b e i st s t e t y i utut i s e t i me s s u n t i n d s f ris e times t e i t s n b e e t e m i n e b y m u t i y ing t e ty i u es es e n t e b y s ing t e u t t e es i e i t i e i i e b y f tbe tyi rise f tim e s i t f c i t i e l e ds se t t ing d s t y p ( n s ) 0 1 3 . 5 1 7 . 2 2 5 0 3 3 . 7 4 3 . 2 5 2 . 8 6 2 . 3 7 2 . 0 syncro niz a tio n usi n g syncb m a n y a p p l ica t i o n s r e q u i r e t h e a b ili t y t o sy n c h r o n iz e o n e o r m o r e AD9864s in a wa y tha t c a us es th e o u t p u t da ta t o be p r e- ci se l y ali g n e d t o a n ext e rn al a s y n c h r o n o us si gnal . f o r exa m p l e , receiver appl ica t ions e m ploy i n g div e rsity ofte n require sy n- chronization of multiple ad98 64s d i gi ta l out p ut s. sa te lli te co mmu nic a tio n applica t io ns us ing tdm a me t h o d s may r e quir e sy nchr o n i zat io n b e tw ee n pay l o a d bur s t s to co mpens a te for reference frequency drift and doppler effec t s. syncb c a n be used for this pu rpose. it is an ac tive-low sig n al tha t clears t h e c l ock counters i n both t h e deci matio n filter and the ssi port. th e counters i n t h e clock sy nt hesi zers are not rese t becaus e it is pre s ume d th at the clk si gn als of mult iple ch ips wo uld b e co nn e c ted. s y n c b al so r e sets th e mo dula to r , r e sult- ing i n a large - sc ale i m pulse th at must propag at e through t h e AD9864s dig i tal filter and ssi data formatting c i rcuitry before recoverin g valid output d a ta. as a result, data samples u n af- fected by th is s y ncb in duce d impuls e ca n be r e co ver e d 12 o u tput da ta s a mples after sy ncb go es hig h (ind epe nde nt o f the deci matio n factor). f i gur e 36 sh ow s t h e ti mi ng re la ti on shi p b e t w e e n syn c b and the ssi ports c l ko ut an d fs sign als. sy nc b is a n asy n c h r o - nous act i ve -low sign al t h at mus t rema in lo w for at leas t h a lf a n input cloc k period, i.e., 1 / (2 f clk ). clkout r e mains high whil e fs rem a i n s low upon s y ncb goi n g low. clko ut will b e com e a c ti v e w i th in on e t o two output clock period s upon syncb returnin g high. fs will re appear several output cycles later , depe nd in g o n the di git a l filter s deci ma ti o n facto r an d t h e ssiord se tti ng . note t h a t for any deci matio n f a ctor and ssiord se tti ng , this del a y is fix e d a n d r e pea t ab le. to ver i fy proper syn c h r on ization , th e fs signals of the multiple ad98 64 dev i ces s h o u ld be mo nito r e d. fs syncb clkou t 04319- 0- 036 f i g u re 36. syncb timing interfacing to dsps the AD9864 co nnec t s directly to an analog devices program- mable digital s i gnal processor (d sp). f i gur e 37 illustrates an example with the blackf in ser i es of adsp-2153 x processors. t h e blackfin dsp series of 16-bit prod ucts is optimized for telecom m u n ic a t ions applica t io ns w i th its dy na mic power ma n - a g em e n t fe at ure, m a k i n g it w e l l s u i t ed for port a b l e rad i o prod - ucts. the code compat ible f a mil y members shar e the fu nda- me ntal core attr ibut es of hi g h p e rformance, lo w power con- sum p tion , and th e ease-of-use ad van t ages of a m i crocon troller instruct ion s e t. AD9864 clkout rsclk pc sck pe sel pd mosi doutbm iso fs rfs doutad r spi ssi adsp-2153x serial port spi-port 04319-0-037 f i g u re 37. e x amp l e of a d 9 8 64 and a d sp-2 15 3x int e rf a c e as shown in f i g u r e 37, AD9864 s synchronous serial interface (ssi) links the r e ceiv e data s t re am to t h e dsps serial port (sport). for AD9864 setup and reg i ster prog ramming, the device connects directly to ads p -2153xs spi p o rt. dedic a ted select lines (sel ) allow the ads p -2153x to program and read back reg i sters of multipl e de vi ces usin g on ly on e spi port. the dsp dr i v er co d e per t ai ni ng to t h is i n t e r f ace is a v ail a bl e o n t h e AD9864 web p a ge. rev. 0 page 22 of 44
AD9864 rev. 0 | page 23 of 44 power control to allow power consumption to be minimized, the AD9864 possesses nu me rous spi progra mm abl e power- down an d b i as control bits. the AD9864 powers up with all of its functional blocks plac ed in to a sta n dby sta t e, i.e ., stb y re gister d e faul t is 0x f f . each ma j o r blo c k may t h en b e po were d up by writi n g a 0 to the appropriate b i t of th e stby regist er. thi s sche me pro- vides the greate st flexib ility for configuri n g th e ic to a specif ic applica t io n as w e ll as fo r tailo r i n g th e ic?s po w e r - do w n a nd wake-up c h arac teristics. t a b l e 1 1 summarizes the func tion of each of t h e s t b y bit s . not e that when all the bl ocks are i n standby, the ma ster reference c i rcuit is al so put into st a n dby, and thus the curren t is re d u ced further by 0.4 ma. ta ble 11. sta ndby cont rol bits stb bit effect current reduction (ma) 1 ake-p time (ms) 7: ref voltage referen c e off all bi asing s h ut d o wn. 0.6 0.1 ( c ref = 4.7 nf) 6: lo lo synthesizer off, iotl three-state. 1 . 2 n o t e 2 5: cko clock osci llator off. 1.1 note 2 4: ck clock synthe siz e r off, iotc three-state. clock buffer off if ad c is off. 1 . 3 n o t e 2 3: gc gain control dac off. gcp and gcn three- state. 0.2 depends on c gc 2: lnam lna and mizer off. cvm, c vl, an d cif three-state. 8 . 2 2 . 2 1: nused 0: adc adc off clock buffer off if clk synthesizer off vcm three-state clock to the digital filter halted digital outputs static. 9 . 2 0 . 1 notes 1 h en a ll b l ock s a r e i n st a n dby, t h e m a s t e r re fer e n c e ci rc ui t i s a l so put i n t o standby, and thus t h e current is fu rther re duce d by 0.4 m a . 2 ake-up time is depend ent on prog ramming and / or external components . lo snthesier t h e l o s y nt h e si z e r sh ow n i n f i g u r e 3 8 i s a fu l l y p r og ra m m a b l e ph a s e- l o ck ed l o op (p l l ) ca pa b l e of 6.25 khz resolution at input frequencies up to 300 mhz a nd ref e renc e clocks of up to 25 mhz. it co ns ists o f a lo w no i s e dig i t a l ph ase- fr equency detec t or (pfd), a vari abl e outp ut current ch ar ge pump (cp), a 14-bit ref e ren c e d i vider, progra mmabl e a and b counters, and a du al- m odulus 8/9 prescaler. th e a (3-b it) a nd b (13- bit) co unters, in conu n ctio n wi th the dual 8 / 9 mo dul u s pr escaler , i m pleme n t an n d i vi der w i th n = b a . in addition, t h e bit re feren c e counter r coun ter) a l l o w s s e le c t ab le i n p u t re fe re n c e fre u e n c ie s , f re f , at t h e pfd input. a comple t e pll ca n be imp l eme n te d if the s nthes i z e r is use d with an exter n al l oop filter and ol t age controlled o s cillator vco). the a, b, and r counters can be programmed ia t h e follow i ng registers l o a, lob, and l o r. the charg e pu mp output current is programmable ia the loi regis t er from 0.2 ma to .0 ma us ing the euation ( ) ma loi ipump 2 . 0 + = f re f , is buffered an d d i i de d b the a lue hel d i n th e r counter. the internal f re f is th en co mpar e d to a di i d e d e r s io n o f th e v c o fr euenc , f lo . the p h ase / f r euenc de tect o r pr o ides up an d do w n pulses w h o s e wi dth s ar , d e pe nd ing upo n th e differ e nce i n phase and freu e nc of the det e ctors input s i g n als. the up/d ow n pul s es co ntr o l th e c h ar ge pu mp, m ai ng cur r e nt aailable to c h arge the ext e rnal lowpass loop filter when t h ere is a discrep a nc betw ee n th e i n puts of the pfd . th e output of the low pass f i lt er feeds an ext e rnal vc o w h ose output fre uenc, f lo , is d r ien suc h t h a t i t s di i de d do w n er sio n , f lo , matc hes th at of f ref , th us closing th e feedbac loop. th e s nt hesi ze d fr euenc is r e l a te d to th e r e fer e nce fr eue nc and the lo reg i ster conte n ts as follows ( ) ref lo f lor loa lob f + = lob register is an d its alu e m u st alw a s be gr eater t h a n t h a t l o ade d i n to loa . an e x ample ma he lp illust ra te h o w th e a lues of lo a , lob , and lor c a n be s e l e ct ed . co ns i d er a n ap pl ic a t io n e m p l o in g a mhz cr s tal o s c i llator , i.e., f re f = mhz , w i th th e reui r em ent th a t f re f = 0 0 hz and f lo = mh z , i. e., hi g h si d e i n ec t io n wi th f if = 0. mh z and f cl k = ms ps . l o r is se le ct ed t o be 0 suc h that f ref = 00 h z. the ndiider f a ctor is 0 , whic h c a n be rea l i z ed b se le ctin g lo b = and loa = .
AD9864 th e sta b il ity , p h ase no is e, spur per f o r mance, a nd tr ans i e n t response of the AD9864?s l o (and clk) synthesizers are deter m i n e d by t h e exter n al loop filter, th e vc o, the n- div i de factor, and the r e ference frequency, f ref . a good overview of the theory and prac tical impl ement a ti o n of pll synthesizers (fea- tured as a three-part series in a n alo g d i alo g ue) can b e fo und on the analog devic e s we bsi t e . also, a free sof t ware copy of the analog dev i ces? adisi m pll, a pll synthesizer simul a tio n tool, is av ail a ble at w ww. an alog. c om . note that the adf4112 model c a n be us ed as a close ap proximatio n to the AD9864?s lo synthesizer whe n using this software tool. fref 84k ? ? ? vddl /2). note th a t the f ref in put is sle w ra te depe nd en t a nd must b e dr i e n wit h i n put si gn als ex cee d i n g . v/s to ens u re proper snthe si zer operat io n. if th is con d i tion ca nnot be met, an external logic gate c a n be ins e rted prior to the f ref inpu t to suare up th e si gn al, t h us allo win g a n f ref input freuenc approaching dc. fast acquire mode th e fast acquire circuit a tte mpt s to boost the o u tput current whe n t h e ph ase differ e nce b e tw een t h e di vi ded - do w n lo, i.e., f lo , and the di i ded do wn r e fer e nce fr eue nc , i.e., f ref , exceeds the t h res h old determined b the lofa regis t er . the lofa register spec ifie s a diisor for the f ref s i gn al t h at d e ter m i n es t h e period t ) o f th is di i de d do w n clo c . th is pe r i o d def i n e s th e time i n ter al us ed i n t h e fas t ac uire algorit h m to control the charge pump curren t . assum e fo r the mo me nt t h at t h e no m i n a l ch ar ge pump curren t is at its lo w e st s e tti ng, i . e., loi = 0, and de no te this mi ni mu m curren t b i 0 . when the ou tput pulse from the phase co mpara tor exceeds t , t h e output curre nt for the next pulse is 2 i 0 . when the puls e is w i der tha n 2 t , the output current f o r the next pul s e is i 0 , a nd so forth, up to e i ght ti mes t h e mi ni mum output cur r e nt. if t h e no m i n a l ch ar ge pu mp curren t is more than the mi ni mu m alu e , i.e., loi 0, t h e prece d i n g rule is o n l appl ie d if it result s i n a n i n crease in th e ins t a n t a neous charge pu mp current. if the c h arge pu mp current is s e t to its lowest alue loi = 0) and t h e fas t acuire c i rcuit is enabl e d, the ins t antane ous charge pump curren t will neer fall below 2 i 0 whe n th e pulsewidth is l e ss than t . thus, the c h arge pump curren t when fast acu ire is e n a b led is gi e n b ( ) [ ] t pulsewidth loi max i i 0 fa C pump / , , = = lor /. ch oosing a larger alu e for lofa wil l i n crease t . thus, for a gi e n p h as e differe nce b e tw een t h e l o inp u t and t h e f ref in put , th e in stan tan e ous ch arge pump current will b e less t h a n tha t a ail a bl e for a lofa a lue o f lor /. similarl, a smaller alue for lofa will decreas e t , main g more curren t a ail a bl e for the sa me phase d i fferen c e. in other words, a smaller a lu e of lofa will enable the s nthesizer to settle fa ster in response to a freuenc hop th an will a l a rge lofa a lu e. care must be ta e n to c h oose a alu e for lofa th at is l a rge e n ough alues g r eater t h a n recomme nded) to preent the loop from oscillatin g bac and forth in respo n se to a freuen c hop. table 2. spi r e gisters associ ated with lo snthe size r addres s (hex) bit breakC do wn width defau l t value name 0 x 0 0 ( 7 : 0 ) 1 0 x f f s t b y 0 x 0 8 ( 5 : 0 ) 6 0 x 0 0 l o r ( 1 3 : 8 ) 0 x 0 9 ( 7 : 0 ) 8 0 x 3 8 l o r ( 7 : 0 ) 0x0a (7:5) (4:0) 3 5 0x5 0x00 loa lob (12:8) 0 x 0 b ( 7 : 0 ) 8 0 x i d l o b ( 7 : 0 ) 0x0c (6) (5) (4:2) (1:0) 1 1 3 2 0 0 0 0 lof loinv loi lotm 0 x 0 d ( 3 : 0 ) 4 0 x 0 l o f a ( 1 3 : 8 ) 0 x 0 e ( 7 : 0 ) 8 0 x 0 4 l o f a ( 7 : 0 ) clock synthesizer th e clock sy nt h e siz e r is a fully programm able i n teg e r-n p ll capabl e of 2.2 khz resolutio n at clock inpu t frequencies up to 18 mhz a nd r e f e r e nce fr eque nc ies up to 25 mh z. it is s i m i lar to the lo synthesizer describe d in f i gur e 38 with the following exceptions: ? ?
AD9864 rev. 0 | page 25 of 44 the 14 -bit ref e r e nce co unter and 13 -bit n-divider co u n ter can be programm ed via re gi ste r s ck r and ckn . the c l oc k fr equ e ncy , f cl k , is r e l a te d to th e r e f e r e nce fr e q ue ncy by t h e e q ua t i o n ( = ) () + =
AD9864 frequency (mhz) 500 100 400 600 200 r esista n c e ( ? addres s (hex) bit breakdown width defau l t value name 0 x 0 0 ( 7 : 0 ) 8 0 x f f s t b y 0 x 0 1 ( 3 : 2 ) 2 0 c k o b 0 x 1 0 ( 5 : 0 ) 6 0 0 c k r ( 1 3 : 8 ) 0 x 1 1 ( 7 : 0 ) 8 0 x 3 8 c k r ( 7 : 0 ) 0 x 1 2 ( 4 : 0 ) 5 0 x 0 0 c k n ( 1 2 : 8 ) 0 x 1 3 ( 7 : 0 ) 8 0 x 3 c c k n ( 7 : 0 ) 0x14 (6) (5) (4:2) (1:0) 1 1 3 1 0 0 0 0 ckf ckinv cki cktm 0 x 1 5 ( 3 : 0 ) 4 0 x 0 c k f a ( 1 3 : 8 ) 0 x 1 6 ( 7 : 0 ) 8 0 x 0 4 c k f a ( 7 : 0 ) f i gure 4 4 . the shunt input resi sta n ce vs. the frequ e ncy of th e a d 9 8 6 4 s if 1 inp u t frequency (mhz) 1.5 100 0.5 2.5 200 capaci t ance (p f ) 0 2.0 1.0 150 50 0 350 300 250 04319-0-045 if lna/mi xe r the AD9864 co ntains a single-e nded l n a followed by a gil - bert-type acti ve mixer, s h own i n f i gur e 43 with the required external co mpo n ents. the lna uses n e ga ti v e sh unt fe e d b a ck to set its inpu t i m peda nce at t h e i f in pin, thus m aki ng it d e pen d - ent o n th e inp u t fr equency . it ca n be mo de led as appr o x i mat e ly 370 ?||1.4 pf ( 20%) below 10 0 mhz. f i gur e 44 and f i gur e 4 5 show t h e equ i valent inpu t i m pe dance versu s frequency char ac- teristics of the AD9864. the increa se in shunt resistance versu s fr equency can b e attr i b ut ed to t h e r e duc t io n in ba nd wi dth , thu s the amou nt of negat i ve fe edbac k of the l n a. note th at t h e input s i g n al into ifin should be ac-coupled via a 10 nf cap a ci- tor since t h e l n a inpu t is se lf-b iasi ng. f i gure 45. the shu n t capa cit a nc e v s . the frequ e ncy of th e a d 9 8 6 4 s if 1 inp u t ifin r bias vddi mxop lo input = 0.3v p-p to 1.0v p-p dc servo loop multi-tanh vi stage cxif mxon cxvm c l l cxvl 2.7v to 3.6v r gain r f 04319- 0- 043 50 ? t h e mixers differen t ial lo port is dri v e n by th e lo buffer stage s h o w n i n f i gur e 43, wh ic h ca n be dr iv en singl e -e nd ed o r differ e nti a l. si n c e it is s e lf-b ias i ng, t h e lo s i gn al level c a n be ac-coupled and range from 0.3 v p-p to 1.0 v p-p with neglig i- ble effect o n performance. the m i xers open -collector outputs, mxop a n d mx on, dr ive an ex ter n al r e so na nt tan k co ns ist i ng o f a differ e nti a l lc ne two r k tu n e d to t h e if o f the b a n d -p ass - ? ad c, i.e. , f if 2_ad c = f clk /8. t h e two ind u ctors provid e a d c bias p a th for the mixer core via a series resistor of 50 ?, which is in clud ed to dam p en th e comm on -m ode respon se. the m i xers output m u st be ac-coupled to th e in put of th e band - pass -? adc, if2p, and if2n via two 100 pf capacitors to ensure proper t u ni ng of the lc center freque ncy. the e x te rna l di ffe r entia l l c tank forms th e res o nan t el emen t for t h e fi rs t res o na tor of t h e band- pa ss - ? m o d u lator, and s o m u st b e tun e d t o the f cl k /8 c e nt er fre q ue ncy of t h e mo du l a tor . the ind u ct ors sh ou ld be ch os en s u ch th at th ei r imped a nc e at f cl k /8 is abou t 1 40, i.e., l = 18 0/ f cl k . an accur a cy of 2 0 % is co ns idered to be adeq u a t e . for ex ampl e , at f cl k = 18 mhz, l = 1 0 h is a goo d ch oi ce . on ce the ind u ct ors h a ve be en se le cted , th e requi r e d tank ca pacitan c e ma y be ca lculated usin g the rela ti on f i g u re 43. si mpl i f i e d sche m a t i c of a d 98 64s lna / m i x e r rev. 0 | page 26 of 44
AD9864 () [ ] = for example, at f cl k = 18 mhz and l = 10 h, a capacitance of 250 pf is needed. however, in or der to accommodate an indu c- tor tolerance of 10, th e ta nk capaci ta nce mu st be a d ust able from 227 pf to 278 pf. selecting an external capacitor of 180 pf ensures that ev e n with a 10 to ler a nce an d str a y capacit a nc es as h i gh as 30 pf, the tot a l cap a c i ta nce w i ll b e le ss tha n t h e mi ni mu m valu e nee d e d by th e t a n k . ex tra cap a cita nce i s sup- plied by the AD9864s on-c hip pr ogrammable capacitor array. since the progr a mmi n g ra nge of the cap a citor array is at l e as t 160 pf, the AD9864 has plenty of ra nge to make up for the tol- erances of low c o st external co mpo n e n ts. no t e th at if f cl k is increased by a f a ctor of 1.44 mhz to 26 mhz s o that f cl k /8 becomes 3 . 25 mhz, reducing l an d c by approximately the same factor (i.e. , l = 6.9 h and c = 120 pf) still satisf ies the re qui r e m en t s sta t ed ab ov e . f i gure 46. equivale nt circuit of si xth o r der band- p ass -? modu lator f i gur e 47 shows the measured power s p ect r al den s ity measured at the o u tput o f the undecimated band-pass -? modulato r. no te that the wide dynamic range ach i eved at the cent er fre q uency, f cl k /8, is achieved once the lc an d rc r e so nator s o f the -? mo dulator have been successfully tuned. the o u t-o f -band no ise i s removed b y the d e cimation filte r s f o ll owin g q u ad rature mixe r. a 16 db st ep at t e nuator is also i n cluded wit h i n the l n a / mixer circuitry to prevent l a rge s i gnals (i.e., C18 db m) from over- dr ivi n g t h e - ? mo dul a to r . in s u ch i n sta n ces , t h e - ? mo dul a - tor will beco me unstable, thus s e verely de sen s it izi n g t h e r e ceiver . th e 16 db step att e nu a t o r can be in vo ked by sett ing the a t ten bit (regist e r 0x03, bit 7), caus ing the mixer gain to be r e duc e d by 16 db. t h e 16 db step at ten u ato r co uld be use d in appl ica t ion s i n w h ich a pote n t ial target or blo c ker sig n al could excee d th e if input cl ip p o int. althoug h t h e l n a w i ll b e d r i v en in t o compre ssi on , it ma y still be possibl e to recover the desire d s i gn al if it is fm. r e fer t o t a b l e 14 to se e the g a i n com - pression charac teristics of th e l n a and mixer wit h the 16 db atte nu ator en ab led. 0 0 10 20 30 50 dbfs/nbw 40 frequency (mhz) 60 70 80 90 100 12 3 4 5 6 7 8 9 2dbfs output f clk = 18mhz nbw = 3.3khz 04319-0-048 table 14. spi r e gisters as soc i a t ed wi th l n a / mixer addres s (hex) bit breakdown idth defau l t value name 0 x 0 0 ( 7 : 0 ) 8 0 x f f s t b 0 x 0 3 ( 7 ) 1 0 atte n f i gu r e 4 7 . mea s u r ed un de ci ma te d s p e c t ra l ou tpu t o f - ? mo dula tor adc w i t h f clk = 1 8 m s p s and n o i s e ba n d wi d t h o f 3. 3 kh z the sig n al tr ans f er function of the AD9864 possesses inherent ant i - a li as filt eri n g by virt ue of t h e cont inuous -t ime portio ns of the loop filter in the band-p ass -? modu lator . f i gur e 48 illus- trates t h i s property by plotti ng the no m i n a l sig n al tr ansfer functio n of the adc for frequencies up to 2 f cl k . the notc hes tha t naturally o c cur for all frequenci e s t h at ali a s to the f cl k /8 pass b a nd are cl early visi ble. ev en at the w i des t bandwi dth s e t- ting , the notc he s are de ep enou gh to provide greater t h an 80 db of alias protection . th us, th e wid e band if filterin g requir e- ments preceding the AD9864 will be determined mostly by the mixers im age b a n d , w h ic h is of fset from th e de sired if i n put frequency by f cl k /4 (i.e., 2 f cl k /8) rather t h a n any al ias i ng associa t e d wi th the a d c. band-pass -? adc the adc of the AD9864 is s h own in f i gur e 46 . the adc con- tains a si x t h or der m u ltibi t band- pa ss - ? m o d u lator tha t a c hi eve s ve ry high ins t anta ne ous d y n a mi c ran g e ove r a na rrow freq ue ncy b a nd. the l oop f i lt er of t h e b a nd-p a ss - ? mo du l a tor c o n s i s t s of tw o co n t in u o us -tim e r e so nators foll o w e d by a discr e t e time r e so nator, wi th ea ch r e so na tor sta g e co ntr i b u ti ng a pai r of comple x poles . the fi rst re s o nator is an e x te rna l l c tank , whi l e t h e s e cond i s an on- c hi p a c ti ve rc fi lt er. the output of th e lc reso na tor is a c - c oupl e d to th e se cond re so na tor i n p u t v i a 1 00 pf cap a ci tor s . the ce nt er fre q u e nc i e s o f t h es e t w o c o nti n uou s - t i m e reso na tors mus t b e tu ne d to f cl k /8 for the ad c to fun c ti on prop- erly . the ce nt er freq ue ncy of t h e dis c re t e - t i m e re sonator auto - ma tically s c a l e s wi th f clk , th us no tunin g is r e quired . rev. 0 page 27 of 44
AD9864 0 ?10 ?20 ?30 ?50 db ?40 normalized frequency (relative to f out ) ?60 ?70 ?80 0.5 0 1.0 1.5 2.0 notch at all alias frequencies 04319-0-049 wh en tu ni ng t h e lc ta nk, th e s a mpl i ng clo c k fr equency mus t be st able an d t h e lna / mixer, l o synthesizer, and adc must all be pl ace d i n stan d b y . large lo and if sig n als present at the inputs of the AD9864 can corrupt the c a libration. these s i gnal s sho u ld b e m i n i mi zed o r d i sa bl ed dur i ng the c a libr atio n sequenc e . tu ni ng is tr igger e d whe n t h e a d c is ta ke n o u t o f standby if the tune_l c b i t of regi s t er 0x1c has been set. this bit will cle a r w h en t h e tu ning o p eratio n is complete (less t h an 6 ms). t h e tu ni ng co des c a n be r e ad fr o m t h e 3 - bi t capl1 (0x1d) and the 6-bi t capl0 (0 x1e) registers. in a s i m i lar ma nner , tun i ng o f th e rc resonator is activated if the tu ne_r c bit of reg i ster 0 x 1c is set w h e n the a d c i s tak e n out of st a n dby. this b i t will cle a r wh en tuni ng i s com- plete. the tuning code can be re ad from t h e c a pr (0x1f) register. se tti ng both t h e tu ne_lc a nd tu ne_rc bi ts tu nes the l c ta nk and the activ e rc r e sonator in suc c ession. during tuni ng, t h e ad c is no t o p er ati o nal a n d ne it he r dat a no r a clo c k is av ail a bl e from th e ssi port . t a b l e 15 lists th e r e co mm en de d sequenc e o f the spi co mm an ds fo r tuning the adc, an d t a b l e 16 lists all of the spi regi s t ers associate d with band-p ass - ad c. f i g u re 48. sig n al tr ans f er fu nct i on of t h e ba nd-p as s - mo dula tor fro m 0 f clk to 2 f clk f i gur e 49 shows the nominal sig n al tr ansfer fu n c tion mag n i - tude fo r fr eque ncies ne ar th e f clk / pass b a nd. the wi dt h of the pass b a nd deter m i n es t h e tr ans f er function droop, but ee n a t the low e st oers a mpl i ng ratio ) where t h e p a ss b a nd e d ges are at f cl k /2 0.00 f cl k ), the gai n a ria t ion is less t h a n 0. db. no t e th at t h e a m o u n t o f atte nua t io n o f fer e d b t h e sig nal tr ansfer fu nction near f cl k / should also be considered whe n deter m i n i n g t h e nar r o w ba nd i f filter ing r e u i r eme n ts pr ece d ing the ad . table 15. tun i ng sequence addres s (hex) value co mments 0 x 0 0 0 x 4 5 lo synthesizer, lna/mixer, and adc are placed in standby. 0 x 1 c 0 x 0 3 set tne l c and tnerc. ai t for clk to stabili z e if clk synthesizer use d . 0 x 0 0 0 x 4 4 take the adc out of standby. a it for 0x1c to clear (6 ms). lna/mixer can now be taken out of standby if ext e rn a l clk vc o or sou r ce use d , t h e clk o s ci lla t o r m u st a l so b e di sa ble d . large if or lo signals can corrupt the c a libration these sig n als sho u ld be di sa ble d duri n g t h e ca li bra t i o n seq u en ce. 0.10 0 5 db 10 normalied freqenc (relative to f clk ) 15 20 0.05 0 0.05 0.10 04319-0-050 tab l e 16. s p i r e gi s t er s a s soc i a t ed wi th ban d - pa ss - ? adc addres s (hex) value width defau l t value name 0 x 0 0 ( 7 : 0 ) 8 0 x f f s t b y 0x1c (1) (0) 1 1 0 0 tune_lc tune_rc 0 x 1 d ( 2 : 0 ) 3 0 c a p l 1 (2:0 ) 0 x 1 e ( 5 : 0 ) 6 0 x 0 0 c a p l 1 (5:0 ) 0 x 1 f ( 7 : 0 ) 8 0 x 0 0 c a p r f i g u re 49. m a g n it u d e of t h e a d c?s sig n al tr ans f er f u nct i on n e a r f clk /8 t u nin g o f t h e - m o d u l a t o r ? s tw o co n t in uo us -tim e r e s o na t o rs is ess e n t ia l i n r e a l izi n g t h e a d c ? s f u l l d y namic ra n g e and m u st be p e r f o r m e d u p o n sys t em sta r t u p . t o facili t a te t u ning o f th e l c ta n k , a ca p a ci t o r a r ra y is in ter n all y co n n ected t o t h e m x op a nd m x on pins. th e c a p a ci t a nce o f t h is a r r a y is p r o g r a mma b l e f r o m 0 pf t o 20 0 pf 20% a n d ca n be p r og rammed ei t h er automatic a lly or manually via th e spi port. the capac i tors of the acti ve rc re sonator are s i mi larly programmable. note that the AD9864 can be pl aced in and out of its standby mode w i t h - o u t r e tuning sin c e the tuning codes ar e stor ed in the spi register s. once t h e ad98 64 has b e e n tu ned, t h e noise fig u re degradation attri b ute d solel y to the te mper ature dr ift of th e lc a nd rc r e so nato r s is mi ni mal. s i nc e th e dr ift o f the rc r e so nato r is actually negl igi b le comp ared t o that of t h e lc resonator, t h e external l a nd c compone n ts ? te mper ature dri f t charac terist ic s ten d to do mi na te. f i gur e 50 sh o w s the degr ad atio n i n no is e figure as t h e pr oduct of the l c value is allow e d to vary from ?12.5% to +12.5 % . note that the n o ise f i gure remain s relatively rev. 0 | page 28 of 44
AD9864 nstnt e ng e i e m suggesting t t mst i ti ns i nt be euie t etune e t e eti n g te m etue nge nf b lc error 9 8 b hz b hz b hz 49 f i gue tyi n i s e fi gu e deg t i n m l n c c m n ent di t cl 8 m s ps if m h z decima tio n fil t er t e e i m t i n ite s n i n f i gu e nsis ts n f cl k / co mplex mix e r an d a c a sca d e o f th ree li ne ar phase fir filt ers dec, dec2, and dec. dec do wn sam p les b a factor of 2 using a fourth o r der comb fil t er . dec2 also uses a fourth order comb filter, but its decimation f a ctor is set b t h e m fiel d of regis t er 0x0. dec is e i t h er a dec i mate b fir filter or a deci ma te b f i r filter , d e pe nd ing o n the alue of the k bi t within reg i ster 0x0. thus, th e com p osite d e cim a tion f a ctor can b e set to eit h er 0 m or m for k eual to 0 or , respectiel. th e output dat a rate f out ) is e ual to th e mo du lator cloc fre uenc f cl k ) di id e d b the dig i tal f i lter s dec i mat i o n f a cto r . due to th e tra n sitio n region as sociate d w i t h th e dec i matio n filters freuenc response, the deci ma tio n fact o r must be selecte d such that f out is eu a l t o or greater tha n tw ice t h e s i g nal ba nd wi dt h. th is e n sur e s lo w a m plitu d e rip p le in the p a ss ba nd along w i t h th e ab ili t to proide furt her applica t ion specific digi tal f i lteri n g prior to de modul a tio n . or cos sin data from ? k = 0, m = ) and a sa m p ling clo c fr e uenc of mhz. in this example, the outpu t data rate f out ) is 20 sps, wit h a usab le compl e x sign al b a n d w i dt h of 0 h z center e d ar o u n d dc. as th is fig u r e sho w s, t h e f i r s t a nd s e co nd alias bands occurring at ee n integ e r multiple s of f out /2) hae the le ast att e nu atio n but proi d e a t lea s t db of atte nuat io n. note t h a t sig n al s falli ng aroun d freuenc offsets th at are o dd int e ger mul t iple s of f out /2 i.e., 0 hz, 0 hz , an d 0 h z) will fall bac i n t o the tra n si tion ba nd of th e digi tal filt er. frequency hz) 0 00 0 0 0 20 20 0 0 0 0 00 fold ing point n k = 0), the pa ss ba nd gai n a r i a tio n i s .2 db w h en dec i m a t i ng b n k = ), the p a ssband gai n ar i at ion i s 0. db. norm al iza t ion of full sc ale a t ba n d center is accura te to wi th in 0. db across all decimat i on mo des. f i gur e an d f i gur e sho w t h e fo lde d fr euenc respon se of the d e cimator for k = 0 and k = , respectiel. re. 0 page 2 of
AD9864 re pge 44 normalied freuency relatie to out b passband gain freuency b 49 normalied freuency relatie to out b 4 6 8 min alias attn 9b 498 f i gu e 4 p ssbn f eueny r e s n se te deim t fi g u e f e d e i m t feueny res n se normalied freuency relatie to out b passband gain ariation 9b 496 ariable gain am plifier operation ith autom a tic gain c o n t rol te a d 9864 nt ins b t ib e gin m i i e ga n i git g a dga n g it t e n e ess y sign e s tim ti n n nt i uit y e ui e t im emen t u t m ti g in nt a gc s s n in f i g u e 8 t e a g c nt i u i t y ie s ig eg ee gmmbiity in g use s t tim ize t e agc es n s e s e s t e a d 98 64 s y n m i ng e gi e n i ti n te g a is g mmb e e b nge n i m e m e n t e i tin t e adc b y u stin g it s us e e e e ne e e ines i ng te a d c s u s e i s eui en t t tt e n u tin g t e si gn an iti n b i git gin n g e i s i ee b y sin g t e ut ut t e e im ti n i te in t e d ga n t e t t sig t ine se in te suy u e n t i e 6 m a is n m d d i n d df s t e g a ng e s m b t b ttenu ti n f i gu e p ssbn f eueny r e s n se te deim t normalied freuency relatie to out b 4 6 8 min alias attn 8b 49 te u s e t e g a is t e te n t e us b e y nmi nge t e ad 986 4 by i ng t e ad c t i gi t i z e e s i e si g n e g e in ut e nge s e s ee e e s i g n in te es e n e g e u n i t e e i n te e es i t ut s tu tin g iin g te a d c te dga is mst useu in etenin g t e y n mi nge in n bn iti n s e ui ing 6bit i n t m t in tese i t i ns unt izt i n n ise esutin g m in ten t un ti n t 6 bits s e s ete n 6 bit i e int s t ess i ng n eg e t e a d 9 864 s e e t i e n i s e i gu e by b me te dga is enb e b y itin g t te agc ie t e ga n t e d ga n e te i n eite us e nt e i b e g in m e ut mti g in nt a gc m e i t is t n ti n g t t te ga imts negigibe se e u n te e si e sig n s its gin i s ie e b n g e ti s is u e t t e bn it te g a be ing ge te t n te n ne te e si e si gn en te e b u t f cl k / ) and remain ing re la tiel ind e pende nt of gain se tting . as a re su l t , p h ase mo dul a te d sig n als s h o u l d e x per i e n ce mini ma l pha s e error as the a g c a ri es th e vga gain whi l e t r a c i ng an in terfer er or th e desi r e d si gnal unde r fadin g co ndi ti o n s. n o te that the e n e lo pe of the s i gnal will s t ill be af fec t e d b the ag c s e tting s . fi g u r e . f o l d e d d e c i m a t o r freuenc respo n se fo r k = 0
AD9864 ga dac ? f cl k /20. the ms b of this register is the bit that ena b les db o f atte nua t io n in the mix e r . th is featur e a llo ws the ad to cope with large leel signals be o nd the vg as range i. e ., C dbm at l n a i n put) to pree n t oerloading of the a d c. th e lower bi ts specif th e at t e nua t io n i n th e rema inder of the s i gn al pa th. if the d v ga i s ena b le d, t h e a t t e nua t io n r a ng e is from C2 db to 2 db since the dvga proides 2 db of dig i tal g a i n . i n t h is ca se, al l b i ts are s i gn ific a n t. how e er, wit h th e dv ga dis a ble d , t h e at tenu atio n r a nge ex ten d s fr o m 0 db to 2 db and onl the lower bits are us eful. f i gur e sh ows th e relation sh ip between th e am oun t of atten u atio n an d the a g c regi ste r setti ng for both cases . agcg setting hex) 2 0 2 0000 agc atte nuation db) fff fff fff fff vga range dvga range only vga enabled dvga and vga enabled 0000 f i gur e . agc gain ra nge c h ar acteristi c s s. agcg register setti ng wi th and wi tho u t dvga ena b led referring to f i g u r e , the g a i n of the vg a is s e t b a n b i t control dac t h at proi d es a co ntrol sig n al to t h e vg a appe ar ing at t h e ga in c o ntrol pin gc p ). for applicati o ns imp l em en t ing automat i c g a i n control, th e dacs ou tput r e sist anc e ca n be re d u ced b a fact or of t o d e cre a se th e a t ta c ti m e of th e agc response for fas t er signal acu is ition . a n extern al capac i tor, cdac, from gcp to analog gr oun d is reuired to sm ooth the dacs ou tput each time it up dates as wel l as t o filter wi deb a n d noise. note t h a t cdac, in co m b in at ion w i t h t h e d a cs pro gr am ma ble o u t p ut r e sist anc e , s e ts th e C db b a nd wi dt h a nd t i me con s ta nt associ a t ed wi th th i s rc n e t w or. a linear es ti mat e of the rece ie d sign al stren g th is performed at th e output of the first d e cim a tion stage dec) an d output of the d v ga if e n abled), as disc ussed in the ag c sectio n. this dat a is a ail a ble as a bit rssi field wit h i n a n ssi frame w i t h 0 correspondi ng to a full scal e sign al for a gi en agc a tte n u a tio n se tti ng. th e rssi fiel d is u p dat e d at f cl k / 0 and can be us ed wit h th e bit at tenu atio n fiel d o r agcg at tenuatio n set t i n g) to deter m ine the absolute sig n al strength. the accurac of the mean rssi re ad ing rel ati e to the if i n put po wer ) depe nds o n the inpu t si gnal s fr euenc o ffset r e lati e to the if freue nc sinc e bot h dec filter s re sponse as well as the a d c s sig n al transfer funct i on atte nuate t h e mixers downco nert e d signal le e l centered at f cl k /. as a result , the esti ma ted s i g n al strengt h of inp u t sig n als fa lli ng wit h i n prox imit to th e if i s reported accu ratel, w h ile tho s e sig n als at incre a si ngl hig h er freuenc o ffsets in cur larger measurement errors. f i gur e 0 shows the n o r m alized error of the rssi read ing as a fu nctio n of the freue n c offset from the if freuenc . note t h a t th e si gnific anc e of th is error becomes apparen t when deter m i n i n g t h e max i mu m i n p u t in terferer o r blo c er) leels wit h th e ag c e n a b led . re. 0 page of
AD9864 me as ure d rs s i e rror b 6 normalied freuency offset in if cl 9 8 4 496 si gn e s ti m ti n t e t e i st e im t i n st g e s t e agc t e i t ut b n i n teees n i n b n s i gns t t u t e ise e t e a d c sig n esti m tin te te d ga s te agc t mi nimi ze t e e ets te 6 b i t tunt i n nis e en t e e s ti mte sig n e e s i tin t e nge t e agc t e a g c us t s t e ga dg a tte nu ti n se t t i n g s t t t e e s tim te si gn e e is e u t t e gmme ee seiie in te ag cr ie te bsut e sig n st e ngt n b e ete m i n e m t e nt ent s te a t t n n rssi ie t t i s i be i n te ssi t m e en e y nigue it i n t is ag c t i ng nge t e 6bi t ue i n te rssi i e e mins nstnt i e t e 8 bit attn i e ies ing t te g a dg a sett ing nte t t t e a t tn ue is b se n t e 8 msb nt i n e in te agcg i e regis t es n 4 f i gue 6 n m i z e r ssi e s n m i z e if fe u e ny oset autom a tic gain c o n t rol agc a es i t i n te ag c nt g i t m n t e us e u stbe metes s fis t nsie te s e in i te i n b n t g et sig n is b i g g e t n ut b n i n t e e es n t e d ga is is be it t e d g a is b e n t bse n y n t e tget sign e m e sue te dec is u s e t nt te g a gin n t e t get sign i be te t te gmme ee ene e e i te sign is t g e t e t ten u t i n is i n es e it tinity ns t nt ete m i n e b y te ag ca se t t ing lge agca ue s esut in ge g in n ges t us i t i n g ng e s in sign s t eng t i te t get s i gn is t sm e ti e t t e e e e ne e e t e tte nu t i n i s e ue but n t e ti n ity ns t nt is et e m ine by b t t e agca n ag cd set t ings te agcd u e is eeti ey subtte m agca s g e agc d esuts in s m e gi n ng e s n tu s s e t i ng i ng sign s t e gi n t e ga n d ga is u tmti y ust e e n t e ag c is enb e i te agcr i e regist e 6 in tis me te gin te g a is ntinuusy ute t f cl k /0 in an att e mpt to e n sure tha t th e maxi mum a n alog s i gnal leel i n to t h e a d c does not ex ceed t h e adc c l ip leel and t h at the rms output l e el of th e ad c is eual to a programmabl e reference le el. wit h t h e d v g a enabl e d, t h e agc control lo op a l so a t te m p t s t o m i n i m i z e th e effe ct s of b i t trun ca ti on n o i s e prior to the ssi output b cont inuousl adusting the dv gas gai n to en sure max i mu m d i gi t a l gain while no t exceeding the programmable referen c e leel. this programmable l e el c a n be set at db, db, db, 2 db , and db belo w th e ad c satu ration clip) l e e l b writ ing alues from to to the bit a g cr fiel d. note tha t th e ad c clip leel is defined to be 2 db below its full sc ale i.e. , C db m a t t h e l n a in p u t fo r a ma t c h e d in p u t an d m a xi m u m a t t e n u a tio n ). i f a g cr is 0, automatic g a in control is disabled. since clipping of t h e adc i n put will degrade t h e s n r performanc e, t h e r e fer e n c e le e l sh o u ld a l s o t a e in t o co n s ide r a t io n t h e p e a t o r m s c h a r act e r i s t ics o f th e ta rg et o r in terferer) sign als. th e b i t code i n th e agc a fie l d sets the r a w b a ndw i dt h of th e agc loop. wit h agc a = 0, th e agc loop ba ndwi dt h is a t its mi ni mu m o f 0 hz, ass u m i ng f clk = mhz. each increment of agca in creases th e loop ban d wid t h b a factor of f cl k /0 therefore, regist e r s associat ed wi th t h e ag c algorith m are u p dat e d at t h is ra te. the number of oerload and adc rese t occurrences w i th in t h e fi nal i / q update ra te of the ad, as well as the agc al u e msb), can be read from th e ssi d a ta upon proper con f iguration. hz mhz f bw agca clk a 2 / 2 / 0 u u ) an d th e co r r e spo ndi ng att a c t i me is a agca a ttack bw t / 2 00 / 2 . 2 2 / u s u ) assuming that t h e loop dnamics are esse nt iall those of a singl e pole sstem. the agc p e rforms di git a l sig n al est i matio n at the output of t h e first dec i mat i on stage de c ) a s well as the dv ga output t h a t follows the l a st deci matio n stag e dec). the r m s power of the i and q sig n al i s esti ma ted b t h e eu a tio n n q abs n i abs n xest ) th e b i t code i n th e agc d fie l d sets the r a tio of the at tac time to th e deca time in t h e a m plitu d e esti matio n circuitr. wh en agcd is zero, th is rat i o is one. i n crem e n ti ng a g cd multiplies the deca time cons tant b 2/2, allo wing a 0 re. 0 page 2 of
AD9864 range in t h e dec a y time rela tiv e to the att a ck t i me. th e dec a y ti me ma y b e co m p uted from ( ) = ( ) < rev. 0 | page 33 of 44
AD9864 normalized frequency offset = ( f in ? f if )/ f clk ?6 0.02 ?12 0 0.04 0 ?3 ?9 0.03 0.01 ?15 0.05 relative to clip point (dbfs) 04319-0-064 option, t h e use of 24-bit dat a is preferable to us ing t h e d v ga . t a b l e 17 i n d i cat e s wh ich agc a values are reas onabl e for various d e cim a tion fact o r s. t h e white cells indicate that the ( d ecim at ion fac t or/agca) com b in at io n works well; the l i ght gray cells in dic a t e r i ng ing an d a n i n cr ea se in the agc s e t t ling ti me; an d the dark gr ay cell s indic a te t h a t th e com b ina t i o n result s in in st ab i l i t y or near i n sta b il it y in th e ag c loop. setti ng a g cf = 1 improves t h time- d omai n be hav i or at t h e exp e nse of i n creas e d spectral spreadi n g. e table 17. agc a lim i ts if the dvga is enabled agca m 4 5 6 7 8 9 1 0 1 1 1 2 1 3 14 15 6 0 0 1 2 0 1 3 0 0 4 5 4 0 8 decima tion fa ctor 9 0 0 e f i gure 63. maxi mu m inte rfer er ( o r bl o c ker) input l e v e l v s . nor m a l i z ed if f r eque ncy offset table 18. spi r e gisters ass o ciat ed wit h a g c addres s (hex) bit breakdown width defau l t value name 0x03 (7) (6:0) 1 7 0 0x00 atte n agcg (14:8 ) 0 x 0 4 ( 7 : 0 ) 8 0 x 0 0 a g c g ( 7 : 0 ) 0x05 (7:4) (3:0) 4 4 0 0x00 agca agco 0x06 (7) (6:4) (3) (2:0) 1 3 1 3 0 0 0 0 agcv agco agcf agcr f i nally , co n s i d e r the cas e o f a st r o ng o u t-o f -ba nd int e r f er er (i.e., C18 dbm to C32 dbm for matc hed if input) that is l a rger than t h e t a rget s i gnal and l a rge enough to be tr acke d by t h e con t rol loop based on th e output of the dec1 . the ab ili t y of the control loop to track t h is int e rferer and set t h e vg a atte nu atio n to prevent clippi ng of the ad c is l i mit e d by the accuracy of the dig i tal s i g n al es t i matio n occurring at the ou tput of dec1. the accuracy of the digit a l sig n al est i mat i on is a functio n of the frequency offset of th e out-of-band in terferer relati ve to t h e i f frequency as s h own in f i gur e 60. interferers at incre a si ngly hig h er frequency o ffsets inc u r larg er measurement errors, poten t ially causin g the con t rol loop to in ad verten tly r e duce t h e a m o u nt o f vga att e nuat io n t h at m a y r e sult in cl ip- ping of the adc. f i gur e 63 shows the max i mum measured int e rferer signal level versus th e normalized if offset frequency (relative to f clk ) tolerated by the AD9864 relative to its max i - mum targe t i n put sig n al le vel ( 0 dbf s C18 d b m). no t e th at t h e in crea se in allow a b l e in t e rf e r er level occurring beyond 0.04 f clk results from the inhe rent sig n al at te nuat ion provi d e d by the adcs signal tr ansf er functio n . system noise figure (nf) versus vga (or agc) control the AD9864 s s y stem noise fig u re is a func tio n of the acg atte nu atio n a n d output sig n al b a n d w i dt h. f i gure 64 plots the no mi n a l sy ste m nf as a fu nctio n o f the agc a t tenu atio n fo r bo th nar r o w- ba nd (20 k h z) a n d wi de ba nd (15 0 khz) mo des wit h f clk 18 mhz. also sh o w n on the plot is th e sn r that would b e obser v ed at t h e outp ut for a C2 dbf s input. the hig h dynamic r a ng e of the adc within the AD9864 ensures that the system nf incr eases gr adu a lly as th e ag c at te nuat ion is incr e a se d. in na r r o w-ba nd (b w 20 khz) mo d e , the sy s t e m noise fig u re inc r eases by les s than 3 db over a 1 2 db agc range, while in wideband (b w 150 khz) mo de, the degrada- tion i s abou t 5 db. as a result, the hig h est ins t ant a neous dynamic r a ng e for the AD9864 occurs with 12 db of agc attenu atio n, since the AD9864 ca n accommodate an additional 12 db peak sig n al level with onl y a moder a te increase in its n o ise floor. as f i gur e 64 shows, the ad986 4 can ac hieve an snr in excess of 100 db in nar r ow-band applicatio ns. to realize the full performance of the AD9864 in such appl ications, it is recom- m e n d e d th at t h e i/ q da t a b e repre s e n te d w i th 24 b i t s . if 16-b i t rev. 0 page 34 of 44
AD9864 applic ati o ns co nside r atio ns dat a is us ed, the effectiv e syste m nf w i ll i n cre a se b e cause of t h e qua n ti za ti on n o i s e pre s en t in the 16- b i t da ta a f te r t r un ca ti on . frequency planning the o frequen c y (andor adc cloc frequency) must be chosen car e fully to pr event no n internally gener a ted spur s fro m mix i ng do n alo n g ith the desir e d signal thus degr ading the snr per formance the maor s o u r ces of spu r s in the ad 9864 are the ad c cloc and digital circuit r y operating at 3 of f c thus the cl oc fre q uenc y (f c ) i s the most important variable in determining hich o (and t h erefore if) frequencies are viabl e 36 4 3 9 8 nois e fire (db) 9 a attenation (db) snr 9dbfs b hz b hz snr 89dbfs b hz snr 9dbfs snr 3db 4396 many appl icat i o ns ha ve freque ncy plans th at t ake ad va nt age o f in dustr y -st a n d a r d if fr equencie s due to t h e l a r g e select io n o f low cost crystal or saw filters. if the sel e cted i f frequency and adc clock rate result in a problem a tic spurious com p on en t, an altern at ive ad c clock rate s h o u ld be s e lect ed by sligh t ly mod i - fying th e deci matio n factor a n d clk synthes i z e r setti ngs (if used) such th at the output sa mple rate re ma ins the s a me. also, applica t ion s requiring a cert ai n degree of tu ni n g range s h ould tak e i n to consi d eratio n th e lo cation and magn itud e of these spur s whe n d e t e r m i n i n g t h e tu ni ng r a nge as w e ll as o p ti mu m if and adc clo c k fr equency . f i gure 64. no m i na l system n o is e figu r e and p e ak s n r v s . agcg setting (f if = 73. 3 5 mh z, f clk = 1 8 m s ps, and 24-b i t i/q d a t a ) f i gur e 65 plots the no mi nal syst em nf wit h 16- bit outpu t data as a fu nctio n o f agc i n bo t h n a r r o w-ba nd an d wid e b a n d mo de. i n w i d e b a n d mo de, t h e nf curve is v i rt ually unch a n ge d relati ve to t h e 2 4 -bi t output dat a bec a use t h e o u tput snr befo re t r un ca ti on i s a l w a ys le ss th an th e 96 d b sn r th a t 16- b it da ta can support. however, in narrow- band mo de, where t h e outp ut sn r approach es or exceed s the sn r th at can be support e d wi th 16-bit data, the degra d a t ion in s y stem nf is mo re severe. fur- ther more, if th e signal processi ng w i th in the d s p adds no ise a t the le vel of an l s b, the syst em noise fig u re can be de graded even more than f i gur e 65 shows. for example, this coul d occur in a f i xed 16-bit dsp wh ose code is no t o p t i m i z e d to pr o c ess the AD9864s 1 6 -bit data with mi nimal qu antizatio n effec t s. to li mi t th e quan tiz a t i o n e ffe ct s within the ad986 4, the 24-bit dat a u ndergoes noise s h ap ing ust prior to 16-bit tru n ca tion, thus r e duci ng t h e i n - b a nd qu a n ti za tio n no ise by 5 db (wi t h 2 o v er sampl i ng). th is ex pla i ns w h y 98.8 dbf s s n r per f o r ma nc e is still ach i ev abl e wit h 16- bit da ta i n a 10 khz b w . f i gur e 66 plo t s the m e asur e d i n -ba nd no is e po wer as a fu nct i o n of the lo frequ e ncy for f clk = 18 mhz a nd an output sig n al ba nd wi dth of 1 50 khz whe n n o signal is prese n t. a n y lo frequency resul t ing in l a rge spu r s should be av oide d. as this figure shows, l a rge spurs result whe n the lo is f cl k /8 = 2.25 mhz a w ay from a har m onic o f 18 mhz , i.e. , n f cl k f cl k /8. also problemat i c are lo freque ncies who s e o d d o r der h a r m o n - ics, i.e. , m f lo , mix with harm o n ics of f cl k to f cl k /8. t h is spur mech a n is m is a result of the mi xer bein g i n tern ally driv en by a squar e d-up ver s io n o f th e lo inpu t co ns is ting o f t h e lo fr equency an d i t s o dd o r d e r ha r m o n ics. t h ese spur fr equencie s can be calcul ated from the relation ( ) = nois e f igure (db) 15 8 14 13 12 11 10 9 sn r = 98. 8db f s bw = 5 0 k h z b w = 1 50 kh z sn r = 83 d b fs sn r = 9 4 .1 db f s bw = 1 0 k h z sn r = 89. 9db f s 16 17 3 6 0 9 12 vg a a tte n uation ( db) 04319 -0-066 a second source of spurs is a large block of dig i tal c i rcuitry that is clocke d at f cl k /3. problem a ti c lo freque ncie s associate d with this spur source are giv e n by 8 / 3 / clk clk clk lo f f n f f + = f i gure 65. no m i na l system n o is e figu r e and p e ak s n r v s . a g cg setti ng (f if = 7 3 .3 5 mhz, f clk = 1 8 m s ps, a n d 16 -bi t i/ q da ta ) rev. 0 page 35 of 44
AD9864 whic h low level spurs can degrade the AD9864s sens itivity performance. despite the many spurs, swee t spots in t h e l o frequency are gener a lly wi de e n o u gh to acco mmo dat e t h e m a x i mu m s i gn al bandwidth of the AD9864. as ev idence of this property, f i gur e 68 sho w s tha t th e i n -b an d no is e is qu ite co nsta nt fo r lo frequencies ranging from 70 m h z to 71 mhz. in-band p o we r (dbfs ) 60 70 80 90 50 0 250 300 200 150 100 50 lo frequency (mhz) 04319-0-067 f i g u re 66. tot a l in- b and no is e + spur pow er wit h no sig n al a ppli e d as a f u nct i o n of t h e lo f r equen c y (f clk = 18 mhz and output s i gn al band width = 150 khz) in-band p o we r (dbfs ) 60 70 80 90 50 0 250 300 lo frequency (mhz) 200 150 100 50 04319-0-068 f i g u re 67. sa me as f i g u re 66 e x c l udi n g lo frequ e nc ies k n own t o pr oduc e l a rg e in-ba n d spu r s rev. 0 | page 36 of 44
AD9864 70.5 70.0 ?50 ?70 ?60 ?90 ?80 71.0 lo frequency (mhz) in-band p o we r (dbfs ) 04319-0-069 f i gure 68. e x pande d view fro m 70 mh z to 71 mh z 90 50 0 ?40 ?20 ?80 ?60 100 if frequency (mhz) dbfs ?120 ?100 60 70 80 d = f clk /4 = 4.5mhz desired responses 04319-0-070 f i g u re 69. r e s p ons e of a d 98 6 4 t o a ? 20 d b m if input wh en f lo = 71. 1 m h z spurious r e sponses the spectral pu rity of the lo (i ncluding its p h ase noise) is an impo r t a n t co n s i d er at io n s i nc e l o spur s can mi x with u n de- sired s i gnals present at the ad9 864s ifin inpu t to produce an in-band response. to demo nstrate the low lo spur level intro- duced within the AD9864, f i gu r e 69 plots the demodul a ted output power as a fun c tion of th e i n put if freq uency for an l o frequency of 71.1 mhz and a cl ock frequency of 18 mhz. the two larg e C 10 dbfs spikes near t h e ce nt er of the plot are the desir e d resp onses at f lo , f if 2_adc , where f if 2_adc = f cl k /8, i.e., at 68.85 mh z and 73.35 mh z. lo spurs at f lo f spur would result in spurio us responses at offsets of f sp u r ar o u nd t h e desire d respons e s. close-in spu r s of this kind are not vis i bl e on the plot, but s m all spurious res p onses at f lo f if2 _ a d c f cl k , i.e., at 50.85 mh z, 5 5 .35 mhz, 86.8 5 mhz, and 91. 35 mhz, are visi ble at t h e C9 0 dbfs level. this dat a i n dicat e s that t h e AD9864 does an excellent job of pr eserving the purity of the l o signal. f i gur e 69 can al so be used to gauge how well the AD9864 rejects u n desire d sig n als . for ex ample , the half-if response (at 69.975 mhz and 72.225 mhz) is approximatel y C100 dbfs, givi ng a s e lect iv ity of 90 db for this spur ious response. the largest spurious respon se at approxim a tely C70 d b fs occurs with input freq uencies of 70.35 mhz and 71.85 mhz. thes e spurs result from third order no nlin eari ty in t h e sig n al pat h (i.e., ab s [3 f lo C 3 f if _input ] = f cl k /8). external passive compone n t re quirements f i gur e 70 shows an ex ample c i r c uit using the AD9864 and t a b l e 19 show s the nominal dc bias voltag es se en at the differ- ent p i ns. the p u rpose is to sho w the various e x ternal p a ssi ve components required by the AD9864, along with nominal dc voltages for troublesh ootin g purposes. mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp vrefn gndl fref gnds syncb gndh fs doutb douta clkout vddh vddd pe vddi if in cxif gndi cxvl lo p lo n cxvm vddl vddp iout l gndp rref vddq iout c gndq vddc gndc cl kp cl kn gnds gndd pc pd 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 AD9864 50 ? ? table 19. nom i nal dc bi as volt ag es pin number mnemonic nominal dc bias (v) 1 mxop vddi C 0.2 2 mxon vddi C 0.2 4 if2n 1.3 C 1.7 5 if2p 1.3 C 1.7 11 vrefp vdda/2 + 0.250 12 vrefn vdda/2 C 0.250 1 3 r r e f 1 . 2 19 clkp vddc C 1.3 20 clkn vddc C 1.3 3 5 f r e f v d d c / 2 41 cxvm 1.6 C 2.0 42 lon 1.65 C 1.9 43 lop 1.65 C 1.9 44 cxvl vddi C 0.05 46 cxif 1.6 C 2.0 47 ifin 0.9 C 1.1 rev. 0 | page 37 of 44
AD9864 the lo, cl k, and ifin sig n als ar e coupled to t h eir respec tiv e inputs u s ing 10 nf capac i tors. th e output of th e m i xer is cou- pled to the inpu t of the adc us ing 100 pf. an external 100 k resistor from the rref pin to gnd s e ts up the AD9864?s in tern al bias curren t s. vrefp and vref n provid e a differen- tial reference voltage to th e AD9864?s - adc and must be decoupled by a 0.01 f different i a l ca p a ci t o r a l on g w i t h tw o 100 pf capacito rs to gnd. the remaining c a pacitors are used to deco uple o t h e r sensi t i ve i n te r n al no des to g n d. althoug h power supply decoupling c a pacitors are not s h own, it is recom m en de d th at a 0.1 f surface-mou n t c a paci tor be placed as close as possibl e to each power suppl y pin for maxi- mum effecti v e n ess. also not s h own is the inpu t imp e danc e matc hing network used to matc h the AD9864 ?s if input to the external if fil t er. lastly, the l oop filter com p onen ts associated wit h th e lo an d cl k sy nt hes i zer s ar e no t sho w n. lc compone n t values for f cl k = 18 mhz are g i ven f i gur e 70. for other clock frequen c ies, th e two ind u ctors and the capaci- tor of th e lc tan k sh ould be scaled in inverse proportion to th e clock. for exam ple, if f cl k = 26 mh z , th e tw o in d u ct ors s h o u ld be = 6.9 h and th e c a p a c i t o r sh o u ld be abo u t 120 pf . a t o ler- a n c e o f 10% is suf f i cien t fo r t h es e co m p on en ts sin c e t u nin g o f th e l c ta nk i s p e rf o r m e d u p o n sys t e m sta r t u p . applic ati o ns sup e rhet ero d yne r e c e iver e x am ple the AD9864 is ell suited for anal og andor dig i tal narroband radio syste m s bas e d on a superhet er odyne rece iver archit ecture the superhet erodyne archit ecture i s noted for achiev ing exceptional dy na mic r a ng e a nd s e lect ivi t y by using to o r mo r e do n co nv er sio n stages to provide ampl ification of t h e t a rget si gnal h ile f i lteri n g t h e undesired sig n al s the AD9864 gr eatly simplif i es the des i gn of these radio syste m s by int e grat ing the c o mplete if strip ( e xcluding t h e o co) h ile pro v id ing an i d i g i tal outpu t (along it h other sy s tem p a r a meter s ) fo r the de mo dul a tio n o f bo t h a n al o g and di git a l modul a ted sig n al s the AD9864 s exceptional dy na mic range often simpl i fies the if f i lteri n g require m en ts and el iminat es the ne ed for an external ac rf inpt preseect fiter tner if crsta or sa fiter dda ?
AD9864 f i gur e 71 shows a typical dual c o nversio n super h eterody n e receiver us ing the AD9864. an rf tuner is u s ed to select and downco nvert th e target s i g n al t o a suit able f i rst if for the AD9864. a pres elect filter may pr ecede the tu ner to limit the rf input to the ba nd of i n teres t . th e output of the tu ner drives an if filter that provides p a rt ial suppression of adjace nt c h an- nels a n d i n terfe r ers that coul d otherwi s e li mi t the rece iver s dy na mic r a ng e. th e co nver s i o n gai n o f the t u ne r sho u ld be s e t such that the p e ak if input sign al level into the AD9864 is no greater than C1 8 dbm to prev ent clipp i ng. the AD9864 down- converts t h e firs t if signal to a s e cond if t h at is exactly 1/8 of the -? ad cs clock rate, i.e., f cl k /8, to simpl i f y the digi tal quad rature demod u lation process. this second if signal is then di giti ze d by th e -? a d c, de mo dul a te d i n to its qua d r a tur e i an d q co mp o n en ts, filt er ed via ma tch i ng de cim a tio n filters, an d reformat te d to en abl e a sy nchronous se rial i n terfac e to a dsp. i n th is e x ample, the AD9864s l o and clk synthes i zers ar e both enabled, requiring some additional passiv e compo n en ts (for th e syn t h e sizers loop filter s a nd clk o s cillato r ) an d a vco fo r the l o sy nth e si zer . note t h a t not al l of the require d decoupli ng cap a citors are shown. refer to the prev ious section and f i gur e 70 for more inform atio n on required ext e rn al pass ive co mponen ts. th e select io n o f the fir s t if fr eq uency is o f te n b a sed o n t h e availabil i ty of low cost standard crystal or saw filters as well as system frequency pla n ni n g co nsi d er a t i o n s . in gen e ra l, crysta l filter s ar e o f te n used fo r nar r o w - ba nd r a d i o s h a v ing c h a n nel bandwidths bel o w 50 khz with ifs below 120 mhz, whil e saw filters are more suite d for chan n e l ba nd wi dth s grea ter th an 50 khz wit h ifs greater t h a n 70 mhz. the ul ti mat e stop- b a n d rejection requir ed by the if filter will depe nd o n how much suppression is required at the AD9864s imag e band resul t ing fr o m do wnco nv er sio n to t h e sec o nd if . t h is im age b a n d is offset from the f i rst if by twic e the seco nd if fr equency (i.e., f clk /4, depend in g o n h i g h - o r lo w-si de i n jec t io n). th e select iv ity a nd ba nd wi dt h o f the if filter wil l depe nd o n both t h e mag n i t ude and freque ncy offset(s) of the adjace nt channel blocker(s) that coul d overdrive the AD9864s inpu t or ge n e ra t e in -b and in t e rm od ula t ion com p on en t s . furt h e r sup- pression is p e rformed within the AD9864 by its inherent band- pass response and dig i tal dec i mati on filters. note that some applica t ion s wil l require ad d i tio n al applica t io n- specific fil t eri n g performed in the dsp that follo ws the AD9864 to remove the ad jace nt c h a n n e l an d/or i m ple m e n t a ma tche d filter for opti- mum s i g n al det e ctio n. the output data rate of the ad9 864, f ou t , sh ould be ch osen to be at l e as t tw ice the b a ndwi dth or symbol rate of the de sire d signal to e n sure tha t th e dec i ma tion fil t ers provide a flat p a ss- band respo n se as well as to allo w for postproce ssing by a dsp. once f out is det e rmi n e d , th e de cimati o n factor of th e digital filters shoul d be set such that the inpu t clock rate, f clk , falls between the AD9864s ra ted operating range of 13 mhz to 26 mhz a nd no significa n t spur ious products relate d to f clk fall within the desir e d pass band, re su lt in g in a reduct i o n in sen s i - tivity performance. if a spurio us compone n t i s found to li mi t the se ns iti v ity p e r f o r mance, th e deci ma tio n f a ct o r can o f ten be mo dif i e d slig htl y to find a spur i o us fr ee pass b a nd. s e lect ing a hig h er f clk is ty pically mo r e de sir a bl e giv e n a c h o i ce, s i nce the first ifs filter ing requireme n ts often depend o n th e tra n si tion region b e tw een the if frequenc y and the image band (i. e ., f cl k /4). lastly, the output ssi clock rate, f clkou t , and d i gi tal driver stre ngth should be set to their lowest po ssible s e tting s to mi ni mi ze t h e p o tent ial har m fu l effects o f dig i t a l i nduce d no is e whil e preserv i ng a relia b le da ta link to th e dsp . note t h a t th e ssicra, ssic r b, and ssiord regi sters, i.e., 0x 18, 0x19, and 0x1a, provide a large de gree of fl exibil ity for optim i z a t i on of the ssi int e rfac e. syncronization of multiple AD9864s some appl icat io ns, such as rece i ver di versity an d be am s t eeri n g , may require two or more AD9864s operating in parall el while ma int a i n i n g sy nchron iz atio n. f i gur e 71 shows an ex ample of how mul t iple AD9864s can be casc aded, with one device s e rv- ing as the maste r and the other dev i ces serv ing as the slaves. i n this examp l e, all of the de vice s have t h e s a me sp i register con- figuratio n si nce they sh are t h e s a me s p i i n terfa c e to the dsp. since the s t ate of each of the AD9864s inter n al counters is unk n ow n upon ini t i a li zat ion, sy nchron iz atio n of the d e vic e s is re qui r e d vi a a sy n c b puls e (s ee f i gur e 36) t o s y n c h r on iz e th eir dig i tal f i lters and ensure precise time al ignme n t of the data streams. althoug h all of the dev i ces sy n t hes i zers are e n able d, t h e lo and cl k sig n al s for the slav e(s ) are deri ved fro m the mast ers syn t hesizers and are referen c ed to an external c r ystal oscillator. all of th e n e cessary extern al co m p on en ts(i.e., loop filters, varactor, lc, and vco) requ ire d to ensure proper closed -loop operation of t h e s e sy nt hesi zers are i n clude d . note t h a t alt h o u gh th e vc o output of the l o synthe si zer is ac-couple d to t h e sla v es lo i n put(s), all of the clk i n puts of the devices mus t be dc -coupled if the AD9864s clk oscill ators are enabl e d. this is bec a use of t h e dc curre nt re quired by t h e c l k os ci l l a t ors i n ea ch d e vi ce . in e s s e n c e , t h e s e n e gat i ve impe dance core s are operati n g in parall el, i n cre a si ng t h e effective q of the lc resonator circuit. r bia s should be s i ze d such that the su m of the oscilla tors d c bias curren t s maintain s a co mmo n- mo de vo lt age o f ar o u nd 1.6 v. rev. 0 | page 39 of 44
AD9864 rev. 0 | page 40 of 44 25 23 24 33 35 31 29 28 43 42 47 19 20 25 23 24 33 31 29 28 19 20 43 42 47 35 vco fs douta clkout f ref clkp clkn lop lon ifin 15 AD9864 master ioutc loop filter 38 ioutc 15 pe pc pd lop lon ifin fs douta clkout syncb to dsp clkp clkn ioutl to dsp from dsp loop filter c var r d r f c p c z 0.1
AD9864 re pge 4 44 co lna mixer if sa i f sa duplexer preselect gain b nf b gain b nf b gain b nf b gain b nf b if amp gain 9b nf 9b gain b nf b mhz dsp or asic 6b pad 4 pe pc pd syncb fs 9 8 douta clout 9 clp cln lop lon 4 4 4 AD9864 master loop filter io 4 pe pc pd lop lon 4 4 ifin 4 AD9864 slae fs 9 8 douta clout syncb 9 clp cln ioutl loop filter c ar r d r f c p c f clk /) a nd the cloc r a te, f clk , and decim a tion factors m u st be selec t e d to ac commodate th e bandwi d th of t h e desire d i n pu t signal. note that the l o snthe si z e r can be di sa b l ed be ca use i t is no lo ng er r e uir ed. since the mixe r does not hae an l o sse s ass o ciate d with the mix ing o p er atio n, the co ner si o n gai n thr o ugh the lna and mix e r is higher re sulting in a nominal input cli p point of C 2 dbm. the snr perfor mance is dependent o n the vga attenuatio n setting, i/q data resoluti on, and output b a ndwidth as sho w n in f i gur e . applicati o ns r e uir ing the highest instantaneo u s d namic r a nge should set the v g a for ma ximum attenuation. also, see ral e x tra decibels in snr per f or mance ca n be gained at lower signal band widths b using 2bit i/ q data.
AD9864 0 105 s nr (db) 95 bw (khz) 85 80 80 120 140 160 40 20 60 100 100 90 min atten with 24-bit i/q data max atten with 16-bit i/q data min atten with 16-bit i/q data max atten with 24-bit i/q data f clk = 18msps 04319-0-075 f i g u re 74. hu ng mixer snr vs. bw and vga layout e x ample, eva l uation board, and software th e ev aluat i on board a n d its ac company i ng sof t ware provi d e a simple way to evaluate the AD9864. the block diagram in f i gur e 75 sh ows th e m a j o r blocks of th e evaluation bo ard , whic h is des i gn ed to b e flexib l e , allo wi ng co nf i g ur atio n fo r differ e nt appl ic atio ns. the power sup p ly distributio n bl ock provides filtered , ad j u st- able voltages to the various su p p ly pins of the AD9864. in the i f i n pu t si g n al p a t h , co mpo n e n t pa ds are a v a i l a bl e to i m pl e m ent di fferent if im ped a nce m a tching n e tw or k s . th e lo and clk s i gn al s can b e e x t e rn a l l y a p p l i e d o r in t e rn al l y d e ri ved f r om a user-sup pl ied v c o modul e interf ac e dau g ht er b o ar d. the r e f e r - e n ce for t h e o n - c h i p l o a n d c l k sy nt h e s i zer s c a n be appl i e d vi a the ex ter n al f re f in p u t o r a n on -b oa rd c r ys tal o s c i lla t o r. the evaluation b o ard is designed to interface t o a pc via a natio n al instruments ni 6533 d i gital io card. an xilinx f p ga formats the data between the AD9864 and digital i/o ca rd. mixer input dut if input lo input vco module interface crystal oscillator (optional) idt fifo power supply distribution eprom clk input fref input nidaq 6 8 -p in conne ctor xilinx sparton fpga AD9864 04319-0-076 f i g u re 75. ev alu a ti on boa r d p l atfo rm software develo ped using nati o n al i n stru ments labview (an d provid ed as microsoft w i ndows executable programs) i s supplied fo r t h e co nfigur at io n o f the spi po r t r e gister s a n d evalu a tio n of the AD9864 outp ut data. these p r ograms have a conve n ie nt gra p hical u s er i n te rface th at allo w s for easy access to the v a r i o u s s p i po r t co nfigu r atio n r e g i ster s an d fr equency an aly s is of th e output d a t a . for more information o n the ad 9864 evaluation boar d, inclu d - ing an ex ampl e layout, pleas e refer to the eval -ad9874eb dat a she e t ( www. an alog.co m /a n a log_root/st a tic / pdf/ tec h support/ad987 4eb_0.pdf ). rev. 0 | page 42 of 44
AD9864 outline dimensions pin 1 indicator top view 6.75 bs c s q 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 1.00 max 0.65 nom 1.00 0.90 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq 0. 25 m i n seating plane compliant to jedec standards mo-220-vkkd-2 f i gure 76. 4 8 -l ead f r a m e chip s c a l e p a ckage lfcs p (c p - 48)d i m ensi ons sho wn in m i l l i m ete r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. ordering guide ad98 64 prod ucts temperature p a ckage package descri ption package outlin e AD9864bcpz* C40c to +85c lead frame chip scale package (lfcsp) cp-48 AD9864bcpzrl * C40c to +85c lead frame chip scale package (lfcsp) cp-48 a d 9 8 6 4 - e b e v a l u a t i o n boar d *th i s i s a lea d free product . rev. 0 | page 43 of 44
AD9864 rev. 0 | page 44 of 44 notes ? 2003 a n alo g devic e s, inc. all rig h ts res e rve d . t r ade m arks a n d re g i s - t e r e d t r ad e m ar ks ar e t h e p r o p e r ty of their respective companies . c04319-0-8/03(0)

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